Firestorm: ST1 (multiple, 1 reg, 8H) measurements

Code:

  st1 { v0.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
61005	28581	214	0	29	0	1	26	0	0	2	0	5018	27940	0	1	23447	1000	1000	1000	5000	5	15914	27860	28237	3	10	1000	1000	2000	28252	28275	1	1	61001	1000	1000	1002	3	4	0	1001	34	1	1	1000	1	0	1	2	13918	10073	7017	3337	11	67	20747	3331	3805	19	66	71	27891	14183	12380	13661	1000	28360	28312	28361	28458	28595
61004	28488	214	0	24	0	0	25	1	0	0	0	5153	28236	0	1	23365	1000	1000	1000	5000	5	15968	28010	28315	3	32	1000	1000	2000	28308	28207	1	1	61001	1000	1000	1002	2	0	0	1001	39	1	4	1000	1	0	1	2	13922	10191	7074	3411	9	73	20631	3398	3810	16	73	66	27958	14605	12343	13715	1000	28475	28330	28321	28318	28611
61004	28861	213	1	27	1	0	26	1	0	1	0	5143	28048	0	0	23586	1000	1000	1000	5000	7	16036	28032	28274	3	10	1000	1000	2000	28263	28182	1	1	61001	1000	1000	1002	2	4	0	1001	37	1	1	1000	0	0	0	0	13791	10111	7189	3407	9	73	20815	3350	3815	18	68	71	27925	14940	12339	14018	1000	28309	28542	28203	28634	28296
61004	28253	212	1	24	0	0	25	0	0	0	0	5180	27929	1	1	23413	1000	1000	1000	5000	5	15949	27910	28329	3	10	1000	1000	2000	28175	28330	1	1	61001	1000	1000	1003	2	0	0	1001	36	1	4	1000	1	0	0	0	13912	10227	7185	3216	11	68	20657	3421	3811	16	63	71	27868	14583	12112	13793	1000	28084	28374	28389	28497	28637
61004	28422	214	0	33	0	0	28	0	0	1	0	5162	28091	1	0	23478	1000	1000	1000	5000	5	15945	28004	28520	3	10	1000	1000	2000	28257	28377	1	1	61001	1000	1000	1002	3	4	0	1001	36	1	4	1000	1	0	1	1	13925	10302	7114	3421	9	67	20610	3394	3815	11	71	65	27908	14232	12177	13644	1000	28219	28237	28230	28508	28540
61004	28237	212	1	21	0	0	23	1	0	2	0	5132	27986	0	0	23661	1000	1000	1000	5000	5	15956	27859	28168	3	10	1000	1000	2000	28210	28231	1	1	61001	1000	1000	1002	2	0	0	1001	3	1	4	1000	0	3	0	0	14016	10348	7105	3346	10	72	20689	3386	3810	18	69	71	27940	13857	12093	13498	1000	28148	28330	28393	28289	28433
61004	28397	212	1	27	1	0	23	0	0	2	0	5150	28117	0	0	23370	1000	1000	1000	5000	6	15961	27857	28308	3	10	1000	1000	2000	28180	28209	1	1	61001	1000	1000	1001	2	0	0	1001	37	1	7	1000	0	3	1	1	13996	10234	7210	3424	12	66	20620	3282	3806	19	67	68	27904	14370	12058	13854	1000	28274	28403	28478	28401	28466
61004	28195	211	0	28	1	0	25	0	0	1	0	5130	28027	1	0	23405	1000	1000	1000	5000	5	15955	27798	28237	3	10	1000	1000	2000	28282	28381	1	1	61001	1000	1000	1002	3	0	0	1001	0	1	10	1000	0	3	0	0	14110	10136	7247	3405	15	73	20673	3465	3818	13	67	69	27856	14333	12060	13487	1000	28357	28236	28297	28245	28666
61004	28473	211	1	28	0	0	24	0	0	0	0	5050	28125	0	1	23435	1000	1000	1000	5000	7	15972	27799	28334	3	10	1000	1000	2000	28102	28181	1	1	61001	1000	1000	1002	2	0	0	1001	36	1	7	1000	1	3	0	0	13985	10420	7195	3467	6	71	20748	3305	3817	23	67	65	27906	13900	12183	14039	1000	28334	28420	28243	28419	28613
61004	28385	212	1	26	1	0	27	1	0	1	0	5125	28077	0	1	23488	1000	1000	1000	5000	7	15975	27849	28424	3	10	1000	1000	2000	28192	28307	1	1	61001	1000	1000	1001	2	0	0	1001	40	4	7	1000	0	0	0	0	13928	10072	7202	3421	8	70	20640	3386	3821	24	67	76	27966	13977	12357	13748	1000	28480	28543	28260	28317	28625

Count: 8

Code:

  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40052	321	0	0	0	0	0	0	0	3	0	0	0	40030	16	16	0	25	80100	100	80000	100	80000	500	1839472	40017	0	40042	40042	29955	3	30000	80100	200	80000	200	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	1	0	0	80002	2	42	0	0	5110	1	16	1	1	40040	0	80000	100	40044	40043	40043	40044	40043
80204	40042	321	0	0	0	0	0	0	3	3	0	0	0	40027	16	16	2	25	80100	100	80000	100	80000	500	1839472	40015	0	40043	40042	29956	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	2	80002	0	0	0	0	5110	1	16	1	1	40051	0	80000	100	40044	40043	40044	40043	40043
80204	40042	322	0	0	0	0	0	0	0	3	0	0	0	40029	16	16	0	25	80100	100	80000	100	80000	500	1839448	40017	0	40042	40042	29955	3	30001	80100	200	80000	200	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	0	5110	1	16	1	1	40039	0	80000	100	40043	40041	40043	40043	40041
80204	40042	321	0	0	0	0	0	0	0	0	0	0	0	40025	16	16	1	25	80100	100	80000	100	80000	500	1840000	40017	0	40044	40043	29956	3	30000	80100	200	80000	200	160000	40043	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	0	5110	1	16	1	1	40040	0	80000	100	40043	40043	40043	40043	40044
80204	40042	321	0	0	0	0	0	0	0	0	0	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839808	40017	0	40049	40042	29955	3	30008	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	0	0	2	80002	2	34	0	0	5110	1	16	1	1	40039	0	80000	100	40043	40043	40043	40043	40041
80204	40042	310	0	0	0	0	0	0	0	9	0	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839832	40017	0	40042	40042	29953	3	30009	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	0	0	0	80002	2	34	0	0	5110	1	16	1	1	40039	0	80000	100	40051	40052	40051	40052	40043
80204	40042	310	0	0	0	0	0	0	0	3	0	1	0	40028	16	16	0	25	80100	100	80000	100	80000	500	1839784	40017	0	40050	40042	29955	3	30007	80100	200	80000	200	160000	40042	40051	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80002	2	0	2	80002	2	34	0	0	5110	1	16	1	0	40047	0	80000	100	40051	40041	40052	40051	40041
80204	40042	311	0	0	0	0	0	0	0	3	0	0	0	40035	16	0	0	25	80100	100	80000	100	80000	500	1839808	40024	0	40042	40040	29955	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80000	1	0	2	80002	2	36	0	0	5110	1	16	1	1	40039	0	80000	100	40052	40050	40051	40051	40043
80204	40042	310	0	0	0	0	0	0	0	3	0	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	40017	0	40042	40042	29955	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	0	0	8	80002	2	34	0	0	5110	1	16	1	1	40051	0	80000	100	40041	40041	40052	40051	40043
80204	40050	311	0	0	0	0	0	0	0	3	0	0	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839352	40024	0	40042	40128	29967	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80002	0	0	2	80002	2	34	0	0	5110	1	16	1	1	40159	0	80000	100	40051	40043	40043	40043	40050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40050	322	0	0	0	0	0	0	0	15	0	0	0	40027	16	16	28	25	80010	10	80000	10	80000	50	1839808	0	40017	40050	40042	29977	16	30150	80010	20	80000	20	160000	40180	40181	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	0	80002	2	34	0	0	5020	2	16	3	3	40157	80000	10	40180	40051	40050	40051	40136
80024	40042	321	0	0	0	0	0	0	0	14	0	0	0	40311	16	16	0	25	80010	10	80000	10	80000	50	1844197	0	40017	40042	40181	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	2	797	80002	2	34	0	2	5020	3	16	3	3	40039	80000	10	40043	40041	40181	40041	40043
80024	40042	322	0	0	0	0	0	0	0	18	0	0	0	40027	16	16	0	55	80010	10	80000	10	80000	50	1839856	0	40017	40050	40042	29977	3	30031	80010	20	80000	20	160000	40040	40049	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	1	0	8	80002	2	34	0	2	5038	3	16	3	2	40039	80000	10	40043	40043	40043	40043	40043
80024	40050	322	0	0	0	0	0	0	0	17	0	0	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839424	0	40017	40051	40042	30071	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	2	80002	2	0	0	0	5020	3	16	3	2	40047	80000	10	40183	40041	40052	40051	40043
80024	40050	323	0	0	0	0	0	0	0	3	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	40025	40040	40189	29984	3	30030	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	0	0	2	80002	2	34	0	0	5020	4	16	3	4	40039	80000	10	40051	40052	40052	40051	40043
80024	40042	322	0	0	0	0	0	0	0	3	0	0	0	40027	16	16	2	55	80010	10	80000	10	80000	50	1839424	0	40017	40042	40042	29975	3	30031	80010	20	80000	20	160000	40042	40050	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	1	0	80002	2	34	0	0	5020	3	16	3	2	40039	80000	10	40051	40051	40050	40051	40043
80024	40042	322	0	0	0	0	0	0	0	601	0	0	0	40436	0	16	2	25	80010	10	80000	10	80000	50	1839692	0	40022	40057	40187	29994	3	30043	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80062	1	1	2082	80122	2	42	0	0	5020	4	16	4	4	40039	80000	10	40194	40055	40043	40043	40044
80024	40042	321	1	0	1	0	0	0	12	17	0	0	1	40032	0	16	0	25	80010	10	80000	10	80000	50	1839934	0	40017	40042	40040	29975	3	30032	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	44	0	0	80002	1	0	5	80002	2	42	0	0	5020	3	16	2	3	40039	80000	10	40043	40043	40043	40044	40041
80024	40043	321	0	0	0	0	0	0	12	0	0	0	0	40028	16	16	1	25	80010	10	80000	10	80000	50	1839448	0	40019	40042	40042	29977	3	30022	80010	20	80000	20	160000	40042	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	1	0	80002	0	0	5	80002	2	42	0	0	5020	3	16	4	3	40039	80000	10	40041	40044	40043	40041	40044
80024	40054	321	0	0	0	0	0	0	0	3	0	0	0	40027	16	16	1	25	80010	10	80000	10	80000	50	1839448	0	40017	40042	40043	29978	3	30022	80010	20	80000	20	160000	40040	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	0	0	5	80000	2	42	0	0	5020	3	16	3	3	40039	80000	10	40043	40041	40043	40043	40043

ST1 (multiple, 1 reg, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations