Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, 2 regs, 1D)

Test 1: uops

Code:

  st1 { v0.1d, v1.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f223a3f464951schedule uop (52)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f696b6d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)f5f6f7f8fd
620062947822810202000000468229208101844920001000100010001000108988000112173102906429304310200010001000200020002927629401116100110001000100000010000001000020012945926768933138269208383201381320608328618164841347714914100010002926929352293012926429375
62004294132272020400000146392911600184202000100010001000100010909800012176002898429279310200010001000200020002931929279116100110001000100002010000031000020013100936869523163365207533193381522608228584163461320414994100010002929929435293002938929343
62004292952282020100000045452932800184272000100010001000100010904800052174202908829435310200010001000200020002921229135116100110001000100002010001001000020013134924069023141168206983300380729687528587161881334715220100010002936429566293792956729336
62004293772282020300000046982907300184192000100010001000100010907800052172102910729563310200010001000200020002933329200116100110001000100002010000001000020012994927069363133166206483203380922728028627161621357015114100010002942829418294702937029397
62004294382281010200000046502913300184652000100010001000100010902800032176202913529408310200010001000200020002928729289116100110001000100000010000031000020013295925168953149171208233163381421707428641164051345315135100010002935729342294122927729355
620042935022820203000000472829166001842120001000100010001000109118000112179402904029429310200010001000200020002930429325116100110001000100000010000001000020013100915169313147267205793179380624627628687161331349714982100010002939729494293692936729309
62004295382282010200000046382916000184582000100010001000100010905800002176602899429284310200010001000200020002921729237116100110001000100003010000001000020013173929469333187266206953212381818708128611165331350515099100010002929329410294802943629379
62004292852282000200001046892919710183852000100010001000100010906800072169602894329411310200010001000200020002930729345116100110001000100003010000001000020013131937469483084273208413263381516677228595163891344414823100010002936729378293672943729454
62004294182282010200001046072911111183452000100010001000100010909800052171202910129320310200010001000200020002936329314116100110001000100003010000001000030013068938769363146165206863129381522697728627164331333314875100010002933529467293512939029398
62004293412282010100001046522908100184562000100010001000100010901800002169202900229383310200010001000200020002925429328116100110001000100222010010211000121112969927169263084169207203215381521697728672161571323915049100010002938229468294612942429436

Test 2: throughput

Count: 8

Code:

  st1 { v0.1d, v1.1d }, [x6]
  st1 { v0.1d, v1.1d }, [x6]
  st1 { v0.1d, v1.1d }, [x6]
  st1 { v0.1d, v1.1d }, [x6]
  st1 { v0.1d, v1.1d }, [x6]
  st1 { v0.1d, v1.1d }, [x6]
  st1 { v0.1d, v1.1d }, [x6]
  st1 { v0.1d, v1.1d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f222324373f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020640246322000000391003973400340002516348610082116800001008000080000500183985664376740021040042400431995909200011601002008000080000200160000160000400494004211802011009910010080000800001008000000008000210280002234051101161140039080000800001004005040050400434004340043
16020440043321000000391003148400281616125161753100811178000010080000800005001839712642942400210400424004219959032000016010020080000800002001600001600004004240042118020110099100100800008000010080000034008000000080002234051102161240046080000800001004004340044400434004440044
1602044004332100000009100145840027161602516113910081268800001008000080000500184810064845240021040042400491996103200011601002008000080000200160000160000400424004911802011009910010080000800001008000000008000200580002034051101162140039080000800001004004440050400444004340043
1602044004332100000000100308040033161602516112510083353800001008000080000500183971264408440021040042400491995903200011601002008000080000200160000160000400424004811802011009910010080000800001008000003600800020028000220051102161240046080000800001004004340043400434004340043
160204400423210000003300031484002816160251636421008223580000100800008000050018397126450344002404004340049199620320000160100200800008000020016000016000040043400521180201100991001008000080000100800000340080002101180002234051101161140039080000800001004004340044400434004440050
1602044004232100000030000254740027160025161596100826428000010080000800005001839712643121400210400424004219959032000016010020080000800002001600001600004004240042118020110099100100800008000010080000034008000200880002234051101162140039080000800001004004940044400434004340049
1602044004332100000021300039734003316160251615471008149380000100800008000050018397126450584002104004340042199590320001160100200800008000020016000016000040048400421180201100991001008000080000100800000010108000200280002034051101161140083080000800001004004440043400434004340043
1602044004932200000015910103943400271616025163248100817768000010080000800005001839712648716400210400494004319959032000016010020080000800002001600001600004004940043118020110099100100800008000010080000038008000200580000234051101251140039080000800001004004440043400444019440043
1602044004232200000063010390340027161602516239310081341800001008000080000500183971264416840021040042400431995903200001601002008000080000200160000160000400424004311802011009910010080000800001008000000008000200580002234051102161240046080000800001004004340044400434004440044
16020440043321000000183000114140027160025161983100818888000010080000800005001839712643943400210400424004219959032000016010020080000800002001600001602404004240043118020110099100100800008000010080000034008000200880002034051101161140040080000800001004004340044400434004340044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)191e1f23373a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600264006131410110190122614003316160251628301082025800001080000800005018397126401861400234004240048199933200321600102080000800002016000016000040042400481180021109101080000800001080014143610800160014800001634000502041664400588000080000104004340043400434005240050
160024400423001000090539004002716160251654071083059800001080000800005018398326561790400334005840043199823200231600102080000800002016000016000040043400481180021109101080000800001080014143600800160017800002341400502061655400468000080000104005040051400614005140060
1600244006129900000303756140027016025164608108369280000108000080000501840288640136040021400424005219984152002316001020800008000020160000160000400434004911800211091010800008000010800141536018001401148000216361400502041643400558000080000104005340052400534005040051
160024400503001010619015391400461616025162523108010680000108000080000501839712654156040021400434004219982320022160010208000080000201600001600004004240059118002110910108000080000108001514360080016001780002234000502071654400398000080000104005940060400594005940051
160024400582991000018029321400351601251639011081566800001080000800005018402886445680400344005940053199873200301600102080000800002016000016000040058400501180021109101080000800001080014143620800160119800021636000502041675400558000080000104004440043400444005040044
16002440042300100003053920400281616025160080108103180000108000080000501839832656177040034400594004319982320023160010208000080000201600001600004004240049118002110910108000080000108001414001800160119800022341400502051666400398000080000104005340043400444004340051
16002440048299000030908560400281616025165407108539480000108000080000501839712652979040023400484004319982320022160010208000080000201600001600004004340042118002110910108000080000108001414360080016011980002234000502041644400468000080000104005940059400604005140048
16002440051300111002103190140035016525162481108203880000108000080000501839904640996040033400504005819994320038160010208000080000201600001600004005040050118002110910108000080000108001415340080016011480002234000502051665400408000080000104004340044400524004440043
16002440048300000003030190400281616025164280108471480000108000080000501839952645921040026400524006019993320029160010208000080000201600001600004005940050118002110910108000080000108001414000800140018800021601420502061664400478000080000104005040050400504006040043
16002440042300100099053920400280160251638731083858800001080000800005018398326561770400344005940043199823200231600102080000800002016000016000040043400491180021109101080000800001080015153600800140118800000341400502051643400468000080000104005340043400434004440060