Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, 2 regs, 2D)

Test 1: uops

Code:

  st1 { v0.2d, v1.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)181e1f223a3f464951schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)f5f6f7f8fd
620052852921115018000104937277442223031200020002000100001516027278202822431020002000400028523282681161001100010002003380200000132000000013664101287106338183719442350438011338362794014584121211376820002818327874282482811028305
62004281902121701620050513028095022318520002000200010000616045279892835931020002000400028407282731161001100010002003200200001220000600137079749715732939351974333173822842422789214300125321360320002842128132282082828128265
620042854521214013000105267281650023253200020002000100006160682779728572310200020004000282992846611610011000100020033412002024200204221351399347199350153519680323838191441412798314673123761408420002844528223282712827128217
620042829121415011000105112282032023189200020002000100005160422785128343310200020004000283402826811610011000100020042402000012200006001367399057169326173919596318138161244412799814552123441385320002860128627285392838828414
6200428223210140180000052322820600231702000200020001000051605827821283033102000200040002826428309116100110001000200320020000042000040013671100727284339843819799325138221142402792314825126181418620002842828496284062818828274
620042829321313016000004940279552023186200020002000100006160552793028384310200020004000283332821911610011000100020032812002117200208221362110167718733706421980834123837645412793914832121441383020002851228428285692819228307
6200428005210160100001051972807820234222000200020001000031606827942282893102000200040002811928356116100110001000200338120020122000082113654102017203333254019873320138311337472793814840125131389720002863128274283172846428533
6200428475213111131002047042801900231822000200020001000051605727922285523332000200040002826428268116100110001000200434020000142000040013911102487340348773819615330038201845372807314439126191353620002848128478282772839528441
6200428277211190190000050502812500235162000200020001000015160582798028283310200020004000283152845911610011000100020033002000002200004001399199477042332123919590324438121242342808814889125981412720002834328193284612830628151
6200428558214130120001048282807700233462000200020001000051606327929283783102000200040002826528429116100110001000200324020020122000042113660105127086322034119678333638311243362792515322125751418720002834228295284262821828462

Test 2: throughput

Count: 8

Code:

  st1 { v0.2d, v1.2d }, [x6]
  st1 { v0.2d, v1.2d }, [x6]
  st1 { v0.2d, v1.2d }, [x6]
  st1 { v0.2d, v1.2d }, [x6]
  st1 { v0.2d, v1.2d }, [x6]
  st1 { v0.2d, v1.2d }, [x6]
  st1 { v0.2d, v1.2d }, [x6]
  st1 { v0.2d, v1.2d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f233f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
16020580225621110000308002516160251601001001600001001600005003679352080017800428004259957360000160100200160000200320000800438004211802011009910010080000800001001600000000160002002160000242051100011611800511600001008004380043800418004380043
160204800426200000003080027161612516010010016000010016000050036794480800188004080042599533600001601002001600002003200008004380043118020110099100100800008000010016000004200160000002160002042051100011611800391600001008004380043800438004380043
16020480042620000001591080025161602516010010016000010216000050036794720800188004280042599533600121601002001600002003200008018180040118020110099100100800008000010016000004210160002225160002042051100011611800401600001008004480044800448004380043
1602048004362100000123080028016125160100100160000100160000500367944808001780042800425995535999816010020016000020032000080043800431180201100991001008000080000100160000042001600022011160002242051100011611800391600001008004480043800438004180043
160204800426200000060080038161612516040210016000010016000050036794480800188004280042599553600001601002001600002003200008004780042118020110099100100800008000010016000004200160002006160002242051100011611800391600001008004380044800448004480044
16020480043621000000308002716062516010010016000010016000050036794720800178004280042601573604611605322001600002003200008004280042118020110099100100800008000010016000004200160002002160002242051100015211800371600001008004380043800438004180043
160204800426200000000080027161602516010010016000010016000050036794720800208004380043599553600011601002001600002003200008004080051118020110099100100800008000010016000004200160002102160002242051100021611800391600001008004580043800438004180043
160204800406210000003080029161612516010010016000010016000050036794480800178004280040599553600001601002001600002003200008004080051118020110099100100800008000010016000004200160000002160002042051100011611800391600001008004580043800558004380043
160204800426200000012308002501602516010010016000010016000050036794480800178004380042599553600001601002001600002003200008004280050118020110099100100800008000010016000004200160002008160002242051100011611800391600001008004380043800438004180041
16020480042621000000018003916160251601001001600001001600005003679352080015800428005459955360000160100200160000200320000800428004211802011009910010080000800001001600000000160002002160002242051100011611800391600001008004480044800448004380044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f22233a3f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
160025800596211100000001900180038161622516001010160000101600005036796920080024800588005859987360039160010201600002032000080051800521180021109101080000800001016001514360016001601291600001636140502011611800480160000108004880053800488005980054
16002480060621111100000190018003216165251600701016000010160000503679692008003380052800535999336004016011820160000203200008005380047118002110910108000080000101600141500116001600391600001436140502011611800560160000108006080062800538005980048
16002480047621120000000180018003716161251600701016000010160000503680197018006680058800586007936003916001020160240203200008005880058118002110910108000080000101600141400016001400211600021636140502011611800480160000108006180053800608004880054
160024800526201000000001900180043161682516001010160000101600005036799560080023800478005959986360032160010201600002032000080059800591180021109101080000800001016001517360116001600321600021636140502011611800490160000108004880060800588005380053
160024800606201010000101800180032161602516001010160000101600005036799080080034800598005259985360032160118201600002032000080059800591180021109101080000800001016001415360016001620261600021638140502011611800550160000108005480055800618005380060
160024800536201010000001900180037016825160010101600001016000050367969200800348005980059599823600321600102016000020320000800598005811800211091010800008000010160014143600160016920141600001636141502011631800480160000108006280192800598005980053
160024800626201000000002000180035161632516001010160000101600005036802440080033800528005259993360027160010201600002032000080052800531180021109101080000800001016001416360116001688119160002160140502011611800500160000108005380059800518005380059
1600248005362011110001019001800441616525160010101600001016000050367990801800278005880061599933600381601182016000020320000800478004711800211091010800008000010160015143601160016370181600021634141502011611800550160000108005380060800518005380053
1600248005262110000000122100180035007725160010101600001016000050367969200800278005880059599943600391600102016000020320240800588005811800211091010800008000010160014143600160016971231600001436140502011611800500160000108005380060800598005380053
1600248005262110010000331400180037151652516001010160000101600005036798600080033800548005259993360030160010201600002032000080052801901180021109101080000800001016001414000160016661181600021636140502011611800480160000108006180053800608006180048