Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, 2 regs, 2S)

Test 1: uops

Code:

  st1 { v0.2s, v1.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f223a3f464951schedule uop (52)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafl1d cache miss st nonspec (c0)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)f5f6f7f8fd
620062940123602030010004746292780018354200010001000100010001090780001121690290562934831020001000100020022000293852930411610011000100010000301000000100020013330938469133249133207323377381010363928621164951318315012100010002950929361293292943729294
6200429400236010200000046512914700184412000100010001000100010900800052171228664294253102000100010002000200029287293481161001100010001000020100000010002001325793076973318803220664338038139383428642161121318714805100010002940929463293512937329368
6200429428235040400001046012923200183892000100010001000100010945800052175329038293019102000100010002000200029353293951161001100010001000020100000010000001316894666956315413520790331838136303228744162981324915002100010002942229348292062944229370
6200429350235030300000046892901900182742000100010001000100010905800052174529014293313102000100010002000200029348293391161001100010001000000100000010000001334595416905316513220842332538184383528709158671333114829100010002936829357294402944429444
6200429505235020200001046572923400184162000100010001000100010906800052177629139293967102000100010012000200029323293151161001100010001000220100000010002001334592866985320413720761327438198363328741159421315014732100010002938829433293252927629344
620042942023501030000890469129240001837620001000100010001000108998000521778291032939631020001000100020002000293702937011610011000100010000201000000100020013157945469813168038207773393382114414528799161301326214866100010002959729525295742953229511
6200429381237020000000147582931901184902000100010001000100010905800022172428995294183102000100010002000200029278292201161001100010001000020100000010002001313292517010316903020662325738147383728641161021283614957100010002933129305293632949529392
6200429398237030000000046102911500183552000100010001000100010902800062169429074293183102000100010002000200029394292761161001100010001000020100000010002001327592716955315703420725334038259373928721158981326914747100010002937829356293932928129521
62004292782350202000010467329149001839920001000100010001000109068000421730289852926231020001000100020002000293752951211610011000100010000001000100100000013045934169583127138207293375381310334028652161641331214613100010002945529363294352950229444
6200429476237030300000047062917901183752000100010001000100010909800062172228971292093102000100010002000200029182291901161001100010001000020100010010002001317494056897312903820649323138167364428485162391327014589100010002929929232292052930829254

Test 2: throughput

Count: 8

Code:

  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f222324373a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160206400583211100000018100127314003516002516319410081233800001008000080000500184002464351540027400584005319959032001616010020080000800002001600001600004005140057118020110099010010080000800001008001514360080016002180002163414051101161140039080000800001004004340054400434004440061
160204400583211000000021000160714004216165251632181008266180000100800008000050018402646462244002140058400421995903200001601002008000080000200160000160000400584005111802011009901001008000080000100800141536008001601178000216340151101161140046080000800001004005340043400534004340059
160204400423221101200030003440040027161602516145810081711800001008000080000500183980864510940021400514005819963072001916010020080000800002001600001600004004340058118020110099010010080000800001008001415360280016121880002163614151101161140049080000800001004006140059400584006040060
1602044006032211000000191002743140045161652516208010082698800001008000080000500183971264571040033400604006119959032001716010020080000800002001600001600004025640043118020110099010010080000800001008001514360280016011980002163414051101161140045080000800001004005140052400524005240060
160204400533221001100019000201614004316160251625681008126880000100800008000050018402886498804003440052400611997103200181601002008000080000200160000160000400524006111802011009901001008000080000100800151436018001600208000216360051101161140058080000800001004006240062400614006140059
160204400483220000000619000261714003616160251635311008135880000100800008000050018397126483524002540049400581997103200161601002008011980000200160000160000400494005811802011009901001008000080000100800141436018001601198000223614051101251140047080000800001004004940061400514005140044
160204400523210100000618000161914004616165251623381008228480000100801168000050018403126469704003340048400421997203200001601002008000080000200160000160000400504004311802011009901001008000080000100800151400080016012080002163614151101161140056080000800001004005940062400594006040060
1602044006132110000000170002877140037161632516301910083096800001008000080000500184040864474340035400534006119970032000716010020080119800002001600001600004005240060118020110099010010080000800001008001414000800160218800022014151281251140237080000800001004005140044400494026340052
1602044006132200001000300099314003216002516128010081514800001008000080000500184026464650140033402544005819975113200111603242008012080000200160000160000402594025411802011009901001008000080000100800141436980800160118800021636140511061063140055080000800001004024740454400434024940044
160204400573231100120010700019181416481616049163012100838148000010080244800005001848364644874400234044740049199621320161160548200800008011920016000016024040058402551180201100991100100800008000010080074153600800740011658006216340351102161140417080000800001004026540248402614044940060

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f2223373f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5e60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002640042322000000300136640029161602516067510813658000010800008000050185404065903800400214004340043199820320034160010208000080000201600001600004004340042118002110910108000080000108000004200800020028000224200502017161117400408000080000104004440044400434004440044
1600244004332200000000044964002816160251645061082495804201080000800005018397126539610040021400434004219982032002416001020800008000020160000160000400424005211800211091010800008000010800000420080002002800022420050209251817400408000080000104004340044400434004440044
1600244004232100010031013504002816160251628521080278800001080000800005018397126492540140021400434004219982032002316001020800008000020160000160000400434004311800211091010800008000010800000420080002002800022000502017161817400408000080000104004340044400444004440044
160024400423220000003003611400281616025161119108261680000108000080000501839712644257004002140042400431998203200231600102080000800002016000016000040043400421180021109101080000800001080000042008000200680002200050209251815400408000080000104004340044400434004440044
1600244004332200000330011094002716160251632211080039800001080000800005018397126516430040021400424004219982032002216001020800008000020160000160000400434004311800211091010800008000010800000420080000002800022420050201516179400768000080000104004440044400434004440044
160024400453220000033006284002816160251638751080978800001080000800005018397126484990040021400454004219982032002216001020800008000020160000160000400424004311800211091010800008000010800000420080002001097800022420050201516179400408000080000104004440044400444004440044
1600244004332100000330010904002801602516137510843718000010800008000050183971264107700400214004340043199820320023160010208000080000201600001600004004340042118002110910108000080000108000004200800000028000224200502017161711400408000080000104004440191400444004440044
1600244004332100000900035984002816160251605881081645800001080000800005018397126534730040021400434004319982032002316001020800008000020160000160000400424004311800211091010800008000010800000420080002005800020420050201616179400408000080000104004340046400434004440044
1600244004432100000630015714002716160251606841081094800001080000800005018397126520780040021400434004219982032002316001020800008000020160000160000400434004213180021109101080000800001080000000080000005800000420050201716917400678000080000104004440044400454004440043
1600244004332200000030038400271616025162071108121280000108000080000501839712642101004002140042400431998203200231600102080000800002016000016000040043400431180021109101080000800001080000000080002202800022420150209161817400398000080000104004440043400444004440043