Firestorm: ST1 (multiple, 2 regs, 4H) measurements

Code:

  st1 { v0.4h, v1.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
62006	29071	235	1	1	0	1	0	0	0	1	0	0	4723	28864	1	0	18256	2000	1000	1000	1000	1000	10905	8000	12	21685	28736	29115	3	28	2000	1000	1000	2002	2000	28977	28962	1	1	61001	1000	1000	1000	7	3	1000	0	395	1000	3	0	0	0	13147	9336	6868	3137	0	46	20470	3226	3816	34	50	53	28529	15922	12790	14881	1000	1000	29014	29122	29366	29124	29187
62004	29010	234	0	0	0	1	1	0	1	1	0	0	4660	28886	0	1	18404	2000	1000	1000	1000	1000	10913	8000	4	21725	29109	29208	3	10	2000	1000	1000	2000	2000	28843	28862	1	1	61001	1000	1000	1000	0	3	1000	0	0	1000	2	0	0	0	13388	9460	7000	3133	0	42	20328	3207	3817	37	48	45	28323	15595	12636	14495	1000	1000	28984	28922	28891	28840	28949
62004	28928	225	0	0	0	0	0	0	0	1	0	0	4698	28688	0	1	17931	2002	1000	1000	1000	1000	10902	8000	12	21727	28637	28970	3	10	2002	1000	1000	2000	2000	28732	28802	1	1	61001	1000	1000	1000	0	3	1000	0	0	1000	2	0	0	0	13270	9622	6899	3207	0	47	20334	3233	3812	39	47	45	28386	15798	12893	14522	1000	1000	28938	28983	28959	29001	28884
62004	28946	224	1	0	1	0	0	0	88	1	0	0	4530	28640	1	1	17977	2000	1000	1000	1000	1000	10906	8000	10	21675	28619	28831	3	10	2000	1000	1000	2000	2000	28736	28879	2	1	61001	1000	1000	1003	0	3	1000	0	6	1000	3	0	0	0	13319	9483	6978	3220	0	44	20229	3269	3823	36	44	39	28355	15892	12857	14294	1000	1000	28936	28872	28896	28858	28916
62004	28938	224	0	0	0	0	1	0	1	1	0	0	4705	28701	0	1	17872	2000	1000	1000	1000	1000	10900	8000	3	21677	28656	28831	3	10	2000	1000	1000	2000	2000	28893	28790	1	1	61001	1000	1000	1004	0	3	1000	0	0	1000	3	0	0	0	13305	9364	6937	3139	0	46	20292	3270	3814	32	43	39	28342	15800	13074	14650	1000	1000	29067	28980	28943	28831	28935
62004	28938	223	1	0	1	0	0	0	89	1	0	0	4555	28985	0	0	18390	2000	1000	1000	1000	1703	10898	8000	6	21683	28662	29054	8	10	2000	1000	1000	2000	2000	29068	28952	1	1	61001	1000	1000	1000	0	3	1000	0	0	1000	3	0	0	0	13245	9329	6905	3128	0	45	20478	3268	3812	41	45	47	28484	15849	12995	14762	1000	1000	29184	29208	29168	29175	29187
62004	29085	234	1	0	0	0	0	9	1	0	0	1	4657	29122	0	1	18667	2000	1000	1000	1000	1000	10907	8000	1	21767	29239	29583	3	10	2000	1000	1000	2000	2000	29537	29469	1	1	61001	1000	1000	1000	0	2	1000	0	0	1000	2	0	0	0	13303	9490	6928	3203	4	45	20924	3186	3817	31	44	46	28820	16255	13697	14993	1000	1000	29475	29450	29547	29624	29397
62004	29529	229	0	1	2	0	0	0	0	0	0	1	4612	29222	0	0	18463	2000	1000	1000	1000	1000	10898	8000	3	21743	29055	29569	3	10	2000	1000	1000	2000	2000	29378	29414	1	1	61001	1000	1000	1000	0	0	1000	0	0	1000	2	0	0	0	13287	9304	6903	3116	1	38	20980	3164	3816	25	40	46	28708	16471	13659	14936	1000	1000	29642	29661	29664	29629	29628
62004	29609	230	0	1	1	0	0	0	1	0	0	1	4594	29229	0	0	18553	2000	1000	1000	1000	1000	10901	8000	7	21737	29116	29519	3	10	2000	1000	1000	2000	2000	29462	29502	1	1	61001	1000	1000	1000	0	0	1000	0	0	1000	0	0	0	0	13194	9450	6942	3125	0	46	20837	3146	3817	33	45	42	28668	16696	13488	15233	1000	1000	29402	29548	29402	29458	29545
62004	29687	229	0	2	0	0	0	0	0	0	0	0	4571	29173	0	0	18645	2000	1000	1000	1000	1000	10902	8000	2	21671	29020	29490	3	10	2000	1000	1000	2000	2000	29310	29302	1	1	61001	1000	1000	1000	0	2	1000	0	0	1000	2	0	0	0	13257	9326	6972	3136	2	37	20824	3144	3818	30	45	41	28748	16282	13518	15083	1000	1000	29502	29457	29478	29524	29512

Count: 8

Code:

  st1 { v0.4h, v1.4h }, [x6]
  st1 { v0.4h, v1.4h }, [x6]
  st1 { v0.4h, v1.4h }, [x6]
  st1 { v0.4h, v1.4h }, [x6]
  st1 { v0.4h, v1.4h }, [x6]
  st1 { v0.4h, v1.4h }, [x6]
  st1 { v0.4h, v1.4h }, [x6]
  st1 { v0.4h, v1.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	23	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160206	40043	322	0	0	0	0	3	0	0	0	0	0	0	971	0	40027	16	16	1	25	161507	100	80837	80000	100	80000	80000	500	1840024	651209	0	40029	40053	40054	19968	0	3	20009	160100	200	80000	80000	200	160000	160000	40050	40052	1	1	80201	100	99	0	100	100	80000	80000	100	80000	0	42	0	0	80000	0	0	5	80002	2	42	0	0	0	5110	1	16	1	1	40040	0	80000	80000	100	40055	40055	40056	41858	40054
160204	40042	322	0	0	0	0	0	0	0	30	3	0	0	2813	0	40028	16	16	0	25	163680	100	81654	80060	100	80000	80000	500	1839712	647228	0	40021	40243	40043	19959	0	3	20000	160100	200	80000	80120	200	160000	160000	40043	40042	1	1	80201	100	99	0	100	100	80000	80000	100	80014	16	0	98	0	80014	0	1	1138	80002	14	44	14	1	0	5110	1	16	1	1	40040	0	80000	80000	100	40051	40063	40052	40252	40055
160204	40255	321	1	0	1	1	0	0	0	3	700	0	0	4316	1	40038	16	16	1	25	161603	100	81659	80000	100	80000	80000	500	1839904	648384	0	40038	40052	40050	19963	0	3	20009	160100	200	80000	80000	200	160238	160000	40050	40051	1	1	80201	100	99	0	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	1105	80002	2	42	0	0	0	5110	1	16	1	1	40043	0	80000	80000	100	40088	40043	40044	40043	40044
160204	40043	321	0	0	0	0	0	0	0	0	3	0	0	1221	0	40174	16	0	2	25	162954	100	82012	80000	100	80000	80000	500	1839712	648408	0	40021	40043	40045	19959	0	3	20000	160325	200	80000	80000	200	160000	160000	40043	40043	1	1	80201	100	99	0	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	0	0	5128	1	25	1	1	40039	0	80000	80000	100	40053	40052	40049	40054	40055
160204	40259	322	1	0	2	0	0	1	0	0	102	1	0	3248	0	40232	16	16	1	46	163885	100	81347	80000	100	80000	80108	500	1839928	644749	0	40025	40053	40053	19966	0	9	20012	160100	200	80000	80000	200	160000	160000	40043	40251	1	1	80201	100	99	0	100	100	80000	80000	100	80000	0	44	0	2	80002	0	0	2	80002	2	42	0	0	0	5110	1	16	1	1	40229	0	80000	80000	100	40267	40052	40053	40054	40055
160204	40048	321	1	1	1	2	0	0	0	0	18	0	0	2672	1	40039	16	0	0	25	162437	100	81574	80000	100	80000	80000	500	1848388	646496	0	40027	40054	40052	19965	0	3	20008	160100	200	80000	80119	200	160000	160000	40050	40053	1	1	80201	100	99	0	100	100	80000	80000	100	80000	0	42	0	0	80000	0	0	2	80062	2	46	0	0	0	5110	1	16	1	1	40039	0	80000	80000	100	40043	40248	40248	40044	40044
160204	40043	321	0	0	0	0	0	0	0	12	3	0	0	3779	0	40028	16	16	0	25	161277	100	81175	80060	100	80000	80000	500	1839712	650643	0	40021	40042	40043	19959	0	3	20001	160100	200	80000	80000	200	160000	160240	40043	40043	1	1	80201	100	99	0	100	100	80000	80000	100	80000	0	42	101	0	80002	1	0	2	80000	2	42	0	0	0	5128	1	16	1	1	40039	0	80000	80000	100	40056	40063	40064	40063	40051
160204	40052	321	1	0	0	1	0	0	0	12	3	0	0	3972	0	40028	16	16	0	25	163522	100	81279	80000	100	80116	80000	500	1839712	643531	0	40021	40042	40046	19959	0	3	20001	160100	200	80000	80000	200	160000	160000	40244	40042	1	1	80201	100	99	0	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	3	80002	2	42	0	0	0	5110	1	16	1	1	40041	0	80000	80000	100	40043	40043	40043	40043	40044
160204	40043	322	0	0	0	0	0	0	0	0	17	0	0	1497	1	40038	16	16	0	25	162193	100	82651	80000	100	80000	80000	500	1839904	650450	0	40038	40054	40050	19968	0	3	20009	160100	200	80000	80000	200	160000	160000	40053	40051	1	1	80201	100	99	0	100	100	80000	80000	100	80014	14	44	0	1	80014	2	1	16	80002	16	45	14	1	0	5110	1	16	1	1	40046	0	80000	80000	100	40055	40055	40055	40055	40050
160204	40062	322	1	1	0	1	0	0	0	0	19	0	0	1555	1	40047	16	16	1	25	161542	100	82571	80000	100	80000	80000	500	1839712	643716	0	40212	40042	40042	19959	0	3	20003	160100	200	80000	80000	200	160000	160000	40043	40043	1	1	80201	100	99	0	100	100	80000	80000	100	80060	0	42	0	0	80000	0	0	32	80062	2	42	0	2	0	5110	1	16	1	1	40040	0	80000	80000	100	40045	40044	40249	40044	40044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160026	40042	310	0	0	0	0	0	0	0	3	0	0	0	3930	0	40028	16	16	0	25	163770	10	80044	80000	10	80000	80000	50	1840024	645121	40021	40043	40043	19982	0	3	20023	160010	20	80000	80000	20	160000	160000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	1	0	2	80000	2	42	0	0	5020	0	0	32	16	0	32	32	40039	80000	80000	10	40043	40043	40044	40044	40044
160024	40043	310	0	0	0	0	0	0	0	3	0	0	0	487	0	40028	16	16	0	25	160057	10	85075	80000	10	80000	80000	50	1839712	643106	40021	40042	40043	19982	0	3	20023	160010	20	80000	80000	20	160000	160000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80000	0	48	0	0	5020	0	0	14	16	0	34	34	40039	80000	80000	10	40044	40043	40044	40043	40044
160024	40042	310	0	0	0	0	0	0	12	3	0	0	0	578	0	40027	0	16	0	25	165400	10	83100	80000	10	80000	80000	50	1839712	655234	40021	40043	40043	19982	0	3	20023	160010	20	80000	80000	20	160000	160000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	0	5020	0	0	35	16	0	32	32	40039	80000	80000	10	40063	40051	40056	40055	40053
160024	40048	311	1	0	1	1	0	0	0	18	0	0	0	3881	1	40047	16	16	1	25	163750	10	84667	80000	10	80000	80000	50	1840120	652009	40025	40054	40052	19986	0	3	20034	160257	20	80000	80000	20	160000	160000	40054	40054	1	1	80021	10	9	10	10	80000	80000	10	80014	14	0	3	0	80016	0	0	19	80002	16	42	14	0	5020	0	0	13	16	0	13	32	40059	80000	80000	10	40055	40051	40055	40054	40055
160024	40053	311	1	0	0	0	0	0	12	19	0	0	0	4260	1	40047	16	16	1	25	162275	10	80597	80000	10	80000	80000	50	1840096	656083	40029	40054	40051	19988	0	3	20034	160010	20	80000	80000	20	160000	160000	40054	40051	1	1	80021	10	9	10	10	80000	80000	10	80014	15	44	0	1	80016	0	0	16	80002	16	44	14	1	5020	0	0	15	16	0	33	34	40615	80000	80000	10	40049	40053	40052	40049	40054
160024	40055	311	1	0	0	1	0	1	33	17	0	0	0	3715	1	40036	16	16	1	25	161059	10	84078	80000	10	80000	80000	50	1840000	646028	40029	40054	40054	19986	0	3	20032	160010	20	80000	80000	20	160000	160000	40062	40054	1	1	80021	10	9	10	10	80000	80000	10	80014	14	44	0	0	80016	0	1	18	80002	16	44	14	1	5020	0	0	33	16	0	33	33	40040	80000	80000	10	40044	40044	40044	40044	40043
160024	40043	310	0	0	0	0	0	0	12	3	0	0	0	1779	0	40027	16	16	0	25	160882	10	85391	80000	10	80000	80000	50	1839712	643000	40021	40042	40043	19982	0	3	20023	160010	20	80000	80000	20	160000	160000	40054	40051	1	1	80021	10	9	10	10	80000	80000	10	80014	14	44	0	0	80016	0	0	19	80002	16	44	14	0	5020	0	0	15	25	0	34	17	40052	80000	80000	10	40054	40054	40052	40052	40054
160024	40054	310	1	0	0	0	0	0	0	128	0	0	0	3576	0	40028	16	0	0	25	164353	10	82317	80000	10	80000	80000	50	1839712	650934	40021	40043	40043	19982	0	3	20022	160010	20	80000	80000	20	160000	160000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	0	5020	0	0	32	16	0	32	14	40051	80000	80000	10	40049	40053	40052	40053	40054
160024	40054	310	1	0	1	1	0	0	0	19	0	0	0	3137	1	40036	16	16	0	25	162094	10	82500	80000	10	80000	80000	50	1840048	650713	40028	40053	40063	19989	0	3	20033	160010	20	80000	80000	20	160000	160000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80000	0	0	2	80002	2	42	0	0	5020	0	0	14	16	0	30	32	40040	80000	80000	10	40043	40044	40044	40043	40043
160024	40042	311	0	0	0	0	0	0	12	3	0	0	0	2508	1	40037	16	16	0	25	162097	10	83944	80000	10	80000	80000	50	1840048	643119	40028	40054	40062	19986	0	3	20033	160010	20	80000	80000	20	160000	160000	40054	40051	1	1	80021	10	9	10	10	80000	80000	10	80014	14	44	2	0	80016	0	0	15	80000	16	44	14	0	5020	0	0	13	16	0	32	32	40041	80000	80000	10	40044	40043	40044	40044	40044

ST1 (multiple, 2 regs, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations