Firestorm: ST1 (multiple, 2 regs, 8H) measurements

Code:

  st1 { v0.8h, v1.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
62005	29650	240	4	1	1	2	2	1	2	3	3	423	177	1	0	4618	29259	2	2	24576	2000	2000	2002	10000	17	16068	28832	29616	3	10	2000	2000	4000	29383	29428	1	1	61001	1000	1000	2000	0	4	2000	1	0	0	2000	2	4	0	13096	9248	6968	3177	0	48	21578	3310	3818	13	46	51	28739	16162	13605	15614	2000	29334	29469	29453	29401	29521
62004	29369	238	1	0	0	0	0	1	0	0	0	15	1	0	0	4688	29093	2	2	24641	2000	2000	2000	10000	2	16060	28616	29351	3	10	2000	2000	4000	29224	29196	1	1	61001	1000	1000	2000	0	6	2000	0	0	0	2000	0	4	0	13178	9433	6939	3127	0	47	20717	3350	3817	12	40	49	28537	16224	13654	15401	2000	29464	29363	29465	29470	29412
62004	29386	237	0	0	0	0	0	0	0	0	0	24	1	0	0	4626	28914	0	0	24298	2000	2000	2000	10000	2	16086	28724	29402	3	10	2000	2000	4000	29214	29225	1	1	61001	1000	1000	2000	0	0	2000	0	0	0	2000	0	0	0	12233	7705	6426	2895	0	49	24038	3417	3820	74	48	51	28935	16236	13683	15628	2000	29405	29408	29320	29451	29245
62004	29425	227	1	0	0	0	0	0	0	0	0	0	0	0	0	4618	28920	0	0	24409	2001	2000	2000	10001	7	16111	28653	29428	3	10	2002	2000	4000	29237	29345	1	1	61001	1000	1000	2000	0	0	2000	0	0	0	2000	0	4	0	13257	9260	7005	3147	0	47	20788	3274	3820	10	42	45	28596	16314	13630	15397	2000	29384	29316	29384	29383	29409
62004	29335	228	0	0	0	0	0	0	0	0	0	0	0	0	0	4703	29068	0	0	24318	2000	2000	2000	10000	1	16061	28508	29366	3	28	2000	2000	4000	29183	29237	1	1	61001	1000	1000	2000	0	4	2000	0	0	3	2000	0	4	0	13045	9201	6974	3112	0	46	20771	3247	3813	15	50	46	28610	16413	13420	15261	2000	29387	29509	29356	29341	29476
62004	29334	228	1	0	0	0	0	0	0	0	0	0	1	0	0	4701	28863	0	0	24231	2002	2000	2000	10000	1	16243	28570	29322	3	28	2000	2000	4000	29232	29255	1	1	61001	1000	1000	2000	0	0	2000	0	0	3	2000	0	4	0	12882	9302	6969	3106	1	46	20850	3283	3815	17	45	45	28599	16156	13447	15432	2000	29317	29337	29409	29512	29312
62004	29332	227	1	0	0	0	0	1	0	0	0	0	1	0	0	4680	28998	0	0	24307	2000	2000	2000	10000	1	16252	28570	29353	3	10	2000	2000	4000	29193	29197	2	1	61001	1000	1000	2000	2	4	2000	0	0	0	2000	0	4	0	13083	9486	6981	3146	1	49	20684	3275	3814	12	45	44	28535	16175	13552	15119	2000	29331	29482	29265	29306	29339
62004	29442	227	1	0	0	0	0	0	0	1	0	12	1	1	0	4683	28901	0	0	24184	2000	2000	2000	10000	1	16076	28656	29393	3	10	2000	2000	4000	29275	29274	1	1	61001	1000	1000	2000	0	0	2000	0	0	0	2000	0	4	0	13306	9507	6893	3139	2	42	20786	3239	3813	12	46	44	28602	16177	13418	15428	2000	29321	29344	29352	29358	29326
62004	29430	228	1	0	0	0	0	0	1	0	0	0	1	0	0	4715	28987	0	0	24272	2000	2000	2000	10000	4	16085	28528	29417	3	10	2000	2000	4000	29269	29152	1	1	61001	1000	1000	2000	0	0	2000	0	0	0	2000	0	4	0	13224	9556	6950	3198	1	45	20683	3371	3814	16	47	46	28680	15997	13668	15737	2000	29270	29478	29357	29332	29377
62004	29329	228	1	0	0	0	0	0	0	0	0	0	1	0	0	4673	28983	0	0	24260	2000	2000	2000	10000	3	16084	28549	29416	3	29	2000	2000	4000	29339	29234	1	1	61001	1000	1000	2000	0	4	2000	0	0	0	2000	0	4	0	13174	9372	6968	3207	0	48	20777	3286	3816	14	41	41	28555	15976	13443	15617	2000	29305	29350	29322	29230	29501

Count: 8

Code:

  st1 { v0.8h, v1.8h }, [x6]
  st1 { v0.8h, v1.8h }, [x6]
  st1 { v0.8h, v1.8h }, [x6]
  st1 { v0.8h, v1.8h }, [x6]
  st1 { v0.8h, v1.8h }, [x6]
  st1 { v0.8h, v1.8h }, [x6]
  st1 { v0.8h, v1.8h }, [x6]
  st1 { v0.8h, v1.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	80042	620	0	0	0	0	0	0	0	0	3	0	0	0	80027	0	16	0	25	160100	100	160000	100	160000	500	3679856	0	80017	80042	80042	59955	3	60000	160100	200	160000	200	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160000	1	2	2	160002	2	34	0	0	0	0	0	5110	1	16	1	1	80048	0	160000	100	80043	80043	80043	80043	80043
160204	80042	621	0	0	0	1	0	0	0	12	3	0	0	0	80036	16	16	0	25	160100	100	160000	100	160000	500	3679856	0	80017	80050	80042	59955	3	59998	160100	200	160000	200	320000	80042	80180	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	2	160000	2	34	0	0	0	0	0	5110	1	16	1	1	80039	0	160000	100	80050	80043	80043	80050	80043
160204	80042	621	0	0	0	0	0	0	0	0	9	0	0	0	80027	16	0	2	25	160100	100	160000	100	160000	500	3679424	0	80017	80051	80050	59955	3	60000	160100	200	160000	200	320000	80040	80049	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	30	0	160002	0	0	5	160002	2	34	0	0	0	0	0	5110	1	17	1	1	80037	0	160000	100	80043	80051	80043	80043	80052
160204	80042	620	0	0	0	0	0	0	0	0	3	1	0	0	80035	16	0	0	25	160100	100	160000	100	160000	500	3679424	0	80017	80042	80049	59955	3	60000	160100	200	160000	200	320000	80040	80050	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	6	160002	2	34	0	0	0	0	0	5110	1	16	1	1	80047	0	160000	100	80043	80052	80181	80456	80051
160204	80040	621	0	0	0	0	0	0	0	0	0	0	0	0	80027	16	16	75	25	160100	100	160000	100	160000	500	3679352	0	80017	80042	80042	59955	3	59998	160100	200	160000	200	320240	80042	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	8	161382	2	34	0	0	0	0	0	5110	1	16	1	1	80039	0	160000	100	80052	80043	80043	80043	80043
160204	80049	620	0	0	0	0	0	0	0	0	3	0	0	0	80050	16	16	0	25	160100	100	160000	100	160000	500	3679424	0	80025	80042	80042	59955	3	60000	160100	200	160000	200	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	5	160002	0	34	0	0	0	0	0	5110	1	16	1	1	80039	0	160000	100	80043	80043	80043	80043	80043
160204	80182	620	0	0	0	0	0	0	0	12	0	0	0	0	80027	16	16	0	25	160100	100	160000	100	160000	500	3679352	0	80024	80042	80042	59953	3	59998	160208	200	160000	200	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160062	1	0	5	160002	0	34	0	0	0	0	0	5110	1	25	1	1	80047	0	160000	100	80041	80041	80041	80043	80129
160204	80049	620	0	0	0	0	0	0	0	132	3	0	0	0	80035	16	16	2	25	160100	100	160000	100	160000	500	3679424	0	80017	80050	80051	59955	3	60000	160100	200	160000	200	320000	80050	80050	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	800	160002	2	34	0	0	0	0	0	5110	1	16	1	1	80039	0	160000	100	80043	80043	80043	80043	80043
160204	80050	620	0	0	0	0	0	0	0	0	3	0	0	0	80035	16	16	2	25	160160	100	160000	100	160000	500	3679424	1	80146	80042	80042	59955	3	60000	160100	200	160000	200	320000	80040	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	0	36	0	0	160002	0	0	5	160002	2	34	0	0	0	0	0	5110	1	16	1	1	80047	0	160000	100	80043	80043	80050	80182	80043
160204	80042	620	0	0	0	0	0	0	0	18	3	0	0	0	80027	16	16	0	25	160100	100	160000	100	160000	500	3679424	0	80017	80180	80049	59955	3	60000	160100	200	160000	200	320000	80051	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	5	160002	2	34	0	0	0	0	0	5110	1	16	1	1	80039	0	160000	100	80043	80041	80052	80043	80043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	80042	620	0	0	0	0	0	0	0	186	17	0	0	0	1	80037	16	0	1	25	160010	10	160000	10	160000	50	3680052	0	80029	80063	80052	59989	3	60022	160010	20	160000	20	320000	80054	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	1	0	160002	0	0	5	160002	4	0	0	0	5020	33	16	32	32	80051	0	160000	10	80055	80065	80054	80055	80048
160024	80055	621	1	0	0	0	1	0	0	375	0	1	0	0	0	80027	16	16	0	25	160010	10	160000	10	160000	50	3679448	0	80017	80040	80180	59977	3	60043	160010	20	160000	20	320000	80047	80047	1	1	80021	10	9	10	10	80000	80000	10	160014	14	44	0	0	160016	1	2	17	160002	16	44	14	1	5020	30	16	34	32	80037	0	160000	10	80041	80043	80043	80041	80043
160024	80042	621	0	0	0	0	0	0	0	408	22	0	0	0	1	80037	16	16	3	25	160010	10	160000	10	160000	50	3680438	0	80022	80053	80052	59989	3	60020	160010	20	160000	20	320000	80043	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160002	0	0	2	160002	2	42	0	0	5020	35	16	34	33	80052	0	160000	10	80055	80055	80053	80055	80064
160024	80054	621	1	0	0	0	0	0	0	447	3	0	0	0	0	80027	16	16	1	25	160010	10	160000	10	160000	50	3684332	0	80017	80042	80040	59989	3	60034	160010	20	160000	20	320000	80047	80054	1	1	80021	10	9	10	10	80000	80000	10	160014	15	44	0	1	160016	0	0	17	160002	16	44	14	0	5020	32	16	35	35	80039	0	160000	10	80043	80043	80043	80044	80044
160024	80042	620	0	0	0	0	0	0	0	576	17	1	0	0	1	80033	16	16	1	25	160010	10	160000	10	160000	50	3679692	0	80027	80054	80059	59987	3	60030	160010	20	160000	20	320000	80181	80040	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160004	0	0	6	160002	2	42	0	0	5020	32	16	32	32	80051	0	160000	10	80055	80064	80055	80055	80064
160024	80055	620	1	0	0	0	1	0	1	519	3	1	0	0	0	80028	16	16	11	25	160010	10	160000	10	160000	50	3679352	0	80017	80043	80042	59977	3	60040	160010	20	160000	20	320000	80052	80052	1	1	80021	10	9	10	10	80000	80000	10	160015	16	52	0	0	160016	1	1	15	160002	16	44	14	1	5020	24	16	24	31	80159	0	160000	10	80044	80043	80043	80184	80043
160024	80042	620	0	0	0	0	0	0	0	468	18	1	0	0	1	80049	16	16	0	25	160010	10	160000	10	160000	50	3679908	0	80029	80047	80054	59987	3	60022	160010	20	160000	20	320000	80040	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160000	1	0	5	160002	2	42	0	0	5020	33	16	33	15	80044	0	160000	10	80065	80053	80056	80064	80048
160024	80052	620	1	0	0	0	1	0	0	492	3	0	0	0	0	80028	16	16	73	25	160010	10	160000	10	160000	50	3679352	0	80018	80042	80043	59977	3	60033	160010	20	160000	20	320000	80054	80054	1	1	80021	10	9	10	10	80000	80000	10	160014	14	44	0	0	160016	1	0	17	160002	16	0	14	1	5020	35	16	33	25	80158	0	160000	10	80043	80043	80041	80179	80044
160024	80043	621	0	0	0	0	0	0	0	513	20	1	0	0	1	80039	16	16	1	25	160010	10	160000	10	160000	50	3680004	0	80022	80054	80054	59987	3	60022	160010	20	160000	20	320000	80040	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	29	0	160000	0	0	5	160002	2	42	0	0	5020	34	16	25	34	80051	2	160000	10	80055	80053	80056	80055	80064
160024	80054	620	1	0	0	0	1	0	0	1587	2379	0	0	0	0	80027	16	0	0	25	160010	10	160000	10	160000	50	3679352	0	80015	80042	80043	59975	3	60034	160010	20	160000	20	320000	80054	80054	2	1	80021	10	9	10	10	80000	80000	10	160015	15	51	0	1	160016	0	1	16	160002	16	44	14	1	5034	36	16	34	33	80051	0	160000	10	80043	80043	80044	80043	80043

ST1 (multiple, 2 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations