Firestorm: ST1 (multiple, 3 regs, 16B) measurements

Code:

  st1 { v0.16b, v1.16b, v2.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
63005	29433	237	4	1	1	0	0	2	0	0	0	6	1	0	0	0	4663	29452	3	3	23524	3000	0	3003	3006	16015	7	17120	0	28883	29751	12	71	3003	3003	6012	29624	29674	3	1	61001	1000	1000	3003	2	9	2	3004	0	6	870	3003	0	6	0	0	149	13242	9296	6865	3149	0	52	21074	3392	3818	15	47	49	28958	16446	13296	14810	3000	29644	29713	29622	30227	29596
63004	29662	238	0	0	1	1	1	0	1	0	0	75	599	0	0	0	4692	30017	3	3	23366	3000	17768	3000	3000	15898	6	17048	6	28803	29452	3	10	3000	3000	6000	29324	29340	1	1	61001	1000	1000	3005	3	6	2	3003	1	0	6	3000	3	9	3	1	0	13028	9388	6977	3155	1	49	20689	3419	3811	38	56	53	29593	16191	13615	14813	3000	29391	29407	29393	29437	29419
63004	29296	227	0	0	1	0	0	1	1	1	0	117	1	0	0	0	4682	29126	0	0	23169	3000	0	3000	3000	15904	7	17044	0	28573	29349	3	10	3000	3000	6000	29231	29179	1	1	61001	1000	1000	3000	0	6	1	3000	0	0	0	3003	0	0	0	0	0	13330	9436	6946	3215	0	47	20654	3302	3817	11	50	49	28528	15902	13242	14657	3000	29424	29361	29398	29269	29249
63004	29428	227	0	1	1	0	1	0	0	0	0	0	89	0	0	0	4607	29267	0	0	23222	3000	0	3000	3000	15905	0	17050	0	28530	29371	3	10	3000	3000	6000	29183	29257	1	1	61001	1000	1000	3000	0	6	0	3000	0	0	3	3003	0	6	0	0	0	13105	9314	6924	3101	0	48	20624	3299	3814	10	47	50	28603	16056	12997	14804	3000	29396	29315	29364	29256	29251
63004	29416	227	0	0	0	0	0	1	1	0	0	426	1	0	0	0	4744	29136	0	0	23109	3000	0	3000	3000	15905	3	17047	0	28670	29364	3	10	3000	3000	6000	29249	29161	1	1	61001	1000	1000	3000	2	9	0	3000	0	0	0	3000	0	9	0	0	0	13077	9456	6923	3131	0	46	20652	3224	3814	3	46	46	28502	16086	13253	14985	3000	29356	29292	29486	29425	29331
63004	29411	227	0	0	0	0	0	0	0	0	1	351	1	0	0	0	4689	29050	3	0	23297	3000	0	3000	3003	15900	3	17044	0	28615	29248	3	10	3000	3000	6000	29187	29164	1	1	61001	1000	1000	3000	2	6	0	3000	0	0	3	3000	0	9	0	0	0	13182	9474	6921	3208	0	51	20608	3261	3819	11	43	49	28639	16174	13126	14712	3000	29350	29284	29321	29328	29225
63004	29396	227	0	0	0	0	0	0	0	0	0	99	1	1	0	0	4564	29112	3	3	23264	3000	0	3000	3000	15903	1	17064	0	28547	29341	3	10	3000	3000	6000	29151	29214	1	1	61001	1000	1000	3000	0	6	0	3001	0	0	0	3000	0	9	0	0	0	13397	9294	6938	3120	0	50	20639	3393	3814	14	46	52	28599	16021	13079	14583	3000	29344	29372	29359	29384	29488
63004	29198	227	0	0	1	0	0	2	0	0	0	363	0	1	0	0	4718	29156	0	0	23239	3000	0	3000	3000	15925	5	17054	0	28645	29465	6	10	3000	3000	6000	29285	29259	1	1	61001	1000	1000	3000	0	9	0	3000	0	0	0	3000	0	6	0	0	0	13375	9517	6984	3122	0	49	20788	3372	3813	10	45	44	28535	16482	13106	14678	3000	29424	29332	29420	29362	29317
63004	29315	227	0	0	0	0	0	1	0	1	0	363	1	0	0	0	4709	29034	0	3	23239	3000	0	3000	3000	15902	17	17025	0	28180	28745	3	10	3001	3000	6000	28589	28737	1	1	61001	1000	1000	3000	0	6	2	3000	0	0	0	3000	2	8	0	2	0	12943	9139	6910	3160	2	55	20125	3252	3815	8	52	48	28224	15796	12709	14314	3000	28850	28784	28613	28843	28827
63004	28867	223	0	0	4	0	0	2	0	0	0	324	1	0	0	0	4651	28844	2	0	23135	3000	0	3000	3000	15897	0	17037	0	28042	28602	3	10	3000	3000	6000	28843	28859	1	1	61001	1000	1000	3000	0	8	0	3000	0	0	2	3002	0	8	0	0	0	13473	9301	7035	3243	1	55	19779	3215	3814	17	49	57	28056	15961	12765	15048	3000	28971	28896	29147	28955	28646

Count: 8

Code:

  st1 { v0.16b, v1.16b, v2.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	120050	899	0	0	0	0	0	12	3	0	0	0	120025	0	16	10	25	240100	100	240000	100	240000	500	5519424	0	120026	120040	120040	89955	3	90000	240100	200	240000	200	480000	120040	120049	1	1	80201	100	99	100	100	80000	80000	100	240000	0	36	0	0	240002	1	0	2	240002	2	34	0	0	0	5110	1	16	2	1	120037	0	240000	100	120041	120043	120043	120052	120041
240204	120051	931	0	0	0	0	0	99	6	0	0	0	120036	16	16	1	25	240100	100	240000	100	240000	500	5519352	0	120017	120042	120051	89955	3	90000	240100	200	240000	200	480000	120042	120040	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240000	1	0	5	240002	0	34	0	0	0	5110	1	16	1	1	120039	0	240000	100	120043	120050	120043	120043	120043
240204	120040	930	0	0	0	0	0	12	3	0	0	0	120027	16	16	0	25	240100	100	240000	100	240000	500	5519424	0	120017	120042	120050	89955	3	90000	240100	200	240000	200	480000	120042	120049	1	1	80201	100	99	100	100	80000	80000	100	240000	0	0	0	0	240002	1	0	5	240000	2	34	0	0	0	5110	2	16	2	1	120039	0	240000	100	120043	120050	120043	120041	120052
240204	120042	931	0	0	0	0	0	12	3	0	0	0	120025	16	0	0	25	240100	100	240000	100	240000	500	5519784	0	124708	120042	120042	89955	3	89998	240100	200	240000	200	480000	120049	120040	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	1	0	2	240002	0	0	0	0	0	5110	1	16	2	2	120048	0	240000	100	120041	120043	120043	120050	120051
240204	120040	931	0	0	0	0	0	12	0	0	0	0	120027	16	16	0	25	240100	100	240000	100	240000	600	5519760	0	120015	120042	120040	89955	3	90000	240100	200	240000	200	480000	120051	120042	2	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	8	240002	2	0	0	0	0	5110	1	16	2	1	120047	0	240000	100	120041	120052	120043	120043	120041
240204	120042	931	0	0	0	0	0	0	6	0	0	1	120025	16	16	0	25	240100	100	240000	100	240000	500	5519424	0	120015	120040	120042	89963	3	90000	240100	200	240000	200	480000	120040	120050	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	2	240002	2	34	4	0	0	5110	1	16	1	2	120037	0	240000	100	120043	120043	120041	120041	120043
240204	120049	931	0	0	0	0	0	0	3	0	0	0	120027	16	0	2	25	240100	100	240000	100	240000	500	5519424	0	120017	120042	120040	89953	3	90000	240100	200	240136	200	480000	120042	120040	1	1	80201	100	99	100	100	80000	80000	100	240000	0	0	0	0	240002	1	0	2	240002	2	40	0	0	0	5128	1	16	1	1	120037	0	240000	100	120041	120043	120043	120052	120182
240204	120051	930	0	0	0	0	0	0	0	0	0	0	120036	16	16	0	25	240100	100	240000	100	240000	500	5519424	1	120017	120042	120042	89962	3	90116	240100	200	240000	200	480000	120042	120049	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	2	5	240000	0	34	0	0	0	5110	1	16	1	1	120037	0	240000	100	120043	120041	120043	120043	120043
240204	120040	931	0	0	0	0	0	0	0	0	0	0	120027	16	0	72	25	240100	100	240000	100	240000	500	5519424	0	120017	120042	120042	90047	3	90000	240100	200	240000	200	480246	120040	120050	1	1	80201	100	99	100	100	80000	80000	100	240060	0	34	0	0	240002	0	0	5	240000	2	34	0	0	1	5110	2	16	1	1	120047	0	240000	100	120051	120043	120043	120051	120043
240204	120040	932	0	0	0	0	0	0	3	0	0	0	120027	0	16	0	56	240100	100	240000	100	240000	500	5519352	0	120025	120042	120040	89955	3	90123	240100	200	240000	200	480000	120042	120040	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	11	240000	2	34	0	0	0	5110	2	16	2	1	120039	0	240000	100	120043	120043	120050	120043	120043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	120042	930	0	0	0	0	0	0	0	0	3	0	0	120027	16	16	0	25	240010	10	240000	10	240000	50	5519424	0	120015	120042	120051	89984	3	90022	240010	20	240000	20	480000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	2	240002	0	34	0	0	5020	4	3	16	3	3	120039	0	0	0	240000	10	120043	120041	120051	120182	120043
240024	120042	964	1	1	0	1	0	1	3	396	97	0	0	120311	16	16	1411	782	241510	11	240060	11	240216	50	5533932	0	120137	120180	120461	90162	40	90255	240335	20	240360	20	480720	120323	120189	3	1	80021	10	9	10	10	80000	80000	10	241202	0	0	58	0	240182	0	0	1627	240122	2	0	0	0	5073	3	3	43	4	5	120157	1	0	0	240000	10	120043	120051	120043	120043	120051
240024	120042	965	0	0	0	0	0	0	0	0	3	0	0	120027	16	16	0	25	240010	10	240000	10	240000	50	5519424	0	120024	120050	120042	89977	3	90022	240010	20	240000	20	480000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240000	1	0	2	240002	2	34	0	0	5020	1	3	16	3	3	120039	0	0	0	240000	10	120043	120043	120052	120043	120043
240024	120042	964	0	0	0	0	0	0	0	0	6	1	0	120027	16	16	0	25	240010	10	240000	10	240000	50	5519424	0	120017	120042	120051	89977	3	90022	240128	20	240000	20	480000	120053	120040	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	2	240002	2	34	0	0	5020	1	3	16	4	3	120039	0	0	0	240000	10	120043	120043	120050	120043	120043
240024	120042	964	0	0	0	0	0	0	0	0	3	0	0	120027	16	16	0	25	240010	10	240000	10	240000	50	5519424	0	120017	120042	120042	89977	3	90029	240010	20	240000	20	480000	120042	120050	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	5	240002	0	34	0	0	5020	0	3	16	3	3	120039	0	0	0	240000	10	120043	120043	120050	120043	120043
240024	120042	964	0	0	0	0	0	0	0	0	3	0	0	120027	16	16	28	25	240010	10	240000	10	240000	50	5519352	0	120025	120040	120042	89977	3	90022	240010	20	240000	20	480000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	2	240002	4	34	0	0	5020	0	3	16	3	3	120039	0	0	0	240000	10	120043	120043	120043	120043	120043
240024	120040	964	0	0	0	0	1	0	0	0	3	0	0	120027	0	16	2	25	240010	10	240000	10	240000	50	5519808	0	120017	120042	120042	89977	3	90022	240010	20	240000	20	480000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	5	240002	2	34	0	0	5020	0	3	16	3	3	120039	0	0	0	240000	10	120050	120043	120043	120052	120041
240024	120040	964	0	0	0	0	0	0	0	0	0	1	0	120035	16	16	0	25	240010	10	240000	10	240000	50	5519424	0	120017	120042	120049	89977	3	90022	240010	20	240000	20	480000	120049	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	5	240002	2	34	0	0	5020	0	3	16	3	3	120039	0	0	0	240000	10	120041	120043	120043	120043	120043
240024	120040	964	0	0	0	0	0	0	0	12	3	0	0	120025	16	16	2	25	240010	10	240000	10	240000	50	5519808	0	120017	120042	120042	89977	3	90022	240010	20	240000	20	480000	120051	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	1	0	2	240002	0	34	0	0	5020	0	3	16	3	3	120037	0	0	0	240000	10	120043	120050	120043	120043	120055
240024	120049	964	0	0	0	0	0	0	0	12	3	0	0	120027	16	0	0	25	240010	10	240000	10	240000	50	5519352	0	120017	120042	120051	89984	3	90030	240010	20	240000	20	480000	120049	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	2	240002	4	0	0	0	5020	0	3	16	3	3	120039	0	0	0	240000	10	120043	120043	120052	120041	120043

ST1 (multiple, 3 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations