Firestorm: ST1 (multiple, 3 regs, 1D) measurements

Code:

  st1 { v0.1d, v1.1d, v2.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	1e	1f	23	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63006	29089	233	10	4	0	3	0	0	12	89	0	4523	29105	3	0	18313	3003	1000	2004	1000	2000	15927	8008	12	21674	28913	29108	10	31	3003	2002	1000	4008	2006	29126	29154	4	1	61001	1000	1000	2002	2	4	2	2003	1	11	385	2000	0	6	2	0	13198	9203	6873	3115	2	55	20686	3282	3818	18	55	53	28455	15854	12893	14379	2000	1000	29128	29187	29113	29063	29127
63004	29396	234	4	2	0	3	1	6	0	1	0	4726	28721	0	0	17828	3000	1000	2000	1002	2000	15910	8000	10	21743	28403	28717	3	28	3000	2000	1000	4000	2000	29199	28744	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	6	2000	0	4	0	0	13120	9232	6946	3153	1	50	20273	3211	3820	15	58	56	28311	15309	12717	14603	2000	1000	28719	28717	28662	28648	28776
63004	28755	222	2	3	0	3	0	0	0	1	0	4760	28615	0	0	17733	3000	1000	2000	1000	2000	15914	8000	10	21757	28503	28794	3	10	3000	2000	1000	4000	2000	28717	28712	1	1	61001	1000	1000	2000	0	0	0	2000	0	0	0	2000	0	0	4	0	13112	9753	6993	3173	2	55	20213	3164	3812	27	60	55	28236	15156	12772	14305	2000	1000	28728	28677	28717	28795	28691
63004	28748	222	3	3	1	3	0	0	9	1	0	4775	28560	0	0	17688	3000	1000	2000	1000	2000	15904	8000	8	21663	28511	28742	3	10	3000	2000	1000	4000	2000	28642	28600	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	3	2000	0	4	0	0	13080	9379	6940	3147	2	44	20159	3205	3818	16	51	57	28277	15559	12728	14815	2000	1000	30310	29974	29248	29459	29329
63004	29375	227	3	4	0	3	0	0	12	1	0	4698	29136	0	0	18251	3000	1000	2000	1000	2000	15903	8000	1	21673	29063	29323	3	10	3000	2000	1000	4000	2000	29164	29311	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	388	2000	0	6	0	0	13180	9382	7019	3144	3	54	20598	3208	3820	15	52	52	28661	16188	13348	14547	2000	1000	29355	29333	29438	29368	29286
63004	29325	227	2	3	0	3	0	0	0	0	0	4670	29188	0	0	18224	3003	1000	2000	1000	2000	15900	8000	4	21700	29041	29411	3	10	3000	2000	1000	4004	2000	29209	29269	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	0	4	0	0	13237	9220	6923	3228	1	50	20651	3134	3818	13	51	52	28681	16149	13115	14721	2000	1000	29281	29336	29332	29237	29200
63004	29257	227	2	4	0	0	0	0	12	1	0	4807	29117	0	0	18340	3003	1000	2000	1000	2000	15906	8000	1	21758	29097	29291	3	30	3000	2000	1000	4000	2000	29167	29278	1	1	61001	1000	1000	2000	0	4	0	2000	1	0	0	2000	0	6	0	0	13096	9549	6940	3179	2	53	20568	3321	3822	18	49	50	28706	16107	12991	14929	2000	1000	29368	29472	29362	29500	29385
63004	29311	228	2	3	1	1	0	0	0	1	0	4674	29168	0	0	18323	3000	1000	2000	1000	2000	15910	8000	5	21777	28899	29276	6	10	3000	2000	1000	4000	2000	29240	29248	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	0	6	0	0	13191	9369	6950	3154	1	50	20706	3301	3827	16	49	50	28675	15980	13047	14784	2000	1000	29352	29488	29545	29340	29479
63004	29378	229	3	5	0	1	0	0	12	1	0	4715	29183	0	0	18371	3000	1000	2000	1000	2000	15905	8000	6	21780	29022	29222	3	10	3000	2000	1000	4000	2000	29284	29233	1	1	61001	1000	1000	2000	0	6	0	2000	0	0	0	2000	0	4	0	0	12947	9192	6974	3123	1	50	20640	3211	3821	12	48	52	28471	16285	13339	14969	2000	1000	29158	29337	29279	29360	29342
63004	29440	227	1	3	0	3	0	0	0	0	0	4702	28980	0	0	18237	3000	1000	2000	1000	2000	15907	8000	0	21694	28988	29247	3	10	3000	2000	1000	4000	2000	29322	29189	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	0	6	0	0	12895	9217	6993	3166	1	49	20523	3161	3819	15	54	52	28544	16266	13382	14860	2000	1000	29326	29503	29315	29317	29334

Count: 8

Code:

  st1 { v0.1d, v1.1d, v2.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	23	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240206	80054	620	0	0	0	0	0	0	0	3	0	32	0	80028	16	16	1	25	240111	100	80560	160000	100	80000	160000	500	3679508	640140	0	80018	80046	80043	49956	3	50012	240100	200	160000	80000	200	320000	160000	80043	80043	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	0	5110	0	1	16	1	2	80052	0	160000	80000	100	80053	80055	80064	80055	80055
240204	80054	620	1	1	0	0	0	0	0	19	0	50	1	80039	0	16	5	25	240682	100	80706	160000	100	80000	160000	500	3680541	640115	0	80027	80054	80055	49968	3	50012	240100	200	160000	80000	200	320000	160000	80066	80063	2	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	6	160002	2	42	0	0	5110	0	1	16	2	1	80051	0	160000	80000	100	80054	80055	80053	80054	80055
240204	80054	620	1	1	1	0	0	0	30	3	0	29	0	80028	16	16	1	25	240628	100	80063	160000	100	80000	160000	500	3679532	640117	0	80018	80043	80043	49966	3	50001	240100	200	160000	80062	200	320000	160000	80043	80043	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	0	5110	0	1	16	2	2	80049	0	160000	80000	100	80055	80064	80055	80055	80044
240204	80043	621	0	0	0	0	0	0	0	3	0	963	0	80028	16	0	1	25	240123	100	80038	160000	100	80000	160000	500	3679508	640126	0	80015	80043	80043	49956	3	50001	240267	200	160000	80000	200	320000	160000	80043	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	5	160002	2	42	0	0	5110	0	1	16	2	1	80049	0	160000	80000	100	80055	80053	80055	80055	80053
240204	80054	620	1	2	1	1	0	0	33	21	0	640	0	80028	16	16	1	25	240156	100	80029	160000	100	80000	160000	500	3679388	640131	0	80018	80043	80043	49956	3	50001	240100	200	160000	80000	200	320000	160000	80043	80043	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	2	160002	2	48	0	0	5110	0	1	16	1	2	80040	0	160000	80000	100	80211	80044	80048	80044	80044
240204	80045	621	0	0	0	0	0	0	0	3	0	8	0	80028	16	16	1	25	240811	100	80564	160000	100	80000	160000	500	3679724	642472	0	80018	80043	80043	49956	3	50001	240100	200	160000	80000	200	320000	160000	80049	80210	1	1	80201	100	99	100	100	80000	80000	100	160000	0	44	0	0	160002	1	0	2	160002	2	0	0	0	5110	0	2	16	1	1	80195	0	160000	80000	100	80044	80044	80214	80044	80044
240204	80043	620	0	0	0	0	0	0	0	3	0	11	0	81415	16	16	1	25	240711	100	80634	160000	100	80000	160000	500	3679532	641833	0	80323	80043	80047	50334	3	50001	240100	200	160243	80000	200	320000	160000	80043	80043	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	0	5110	0	1	16	1	1	80040	0	160000	80000	100	80044	80044	80053	80044	80044
240204	80040	622	0	0	0	0	0	0	12	3	0	31	0	80028	0	16	1	25	240121	100	80524	160000	100	80000	160000	500	3679532	642085	0	80018	80043	80043	49955	3	50001	240100	200	160000	80000	200	320000	160000	80054	80054	1	1	80201	100	99	100	100	80000	80000	100	160014	14	44	0	1	160016	0	0	18	160002	16	46	14	0	5110	0	1	16	1	1	80040	0	160000	80000	100	80044	80044	80041	80043	80044
240204	80151	620	0	0	0	0	0	0	0	3	0	1047	0	80039	16	16	5	25	240141	100	80060	160000	100	80000	160000	500	3680063	640099	0	80029	80054	80054	49965	3	50019	240100	200	160000	80061	200	320000	160000	80055	80054	1	1	80201	100	99	100	100	80000	80000	100	160015	14	44	0	0	160016	0	0	19	160062	16	44	14	0	5110	0	1	16	1	3	80049	0	160000	80000	100	80220	80065	80053	80055	80064
240204	80055	621	1	0	0	0	0	0	0	17	0	854	1	80037	16	16	3	25	240775	100	80031	160060	100	80000	160000	500	3680063	640098	0	80029	80052	80051	49967	3	50021	240100	200	160000	80000	200	320000	160000	80052	80216	1	1	80201	100	99	100	100	80000	80000	100	160014	14	44	0	0	160016	0	1	17	160002	16	44	14	0	5110	0	1	16	1	1	80049	0	160000	80000	100	80055	80065	80053	80055	80064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	23	37	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240026	80043	620	0	0	0	12	3	0	1	80028	16	16	1	25	240672	10	80520	160000	10	80000	160000	50	3679532	641482	0	80015	80043	80043	49978	3	50023	240010	20	160000	80000	20	320000	160000	80043	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	2	160000	0	0	0	5020	5	16	4	4	80040	0	160000	80000	10	80044	80044	80044	80044	80044
240024	80043	621	0	0	0	12	3	0	563	80028	16	16	1	25	240928	10	80006	160000	10	80000	160000	50	3679508	641680	0	80018	80043	80043	49978	3	50022	240010	20	160000	80000	20	320000	160000	80043	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	2	160002	0	42	0	5020	3	16	3	3	80040	0	160000	80000	10	80044	80041	80044	80044	80044
240024	80043	621	0	0	0	0	3	0	557	80032	16	16	1	25	240010	10	80603	160000	10	80236	160000	50	3679532	641746	0	80018	80043	80043	49978	3	50023	240010	20	160000	80000	20	320000	160000	80043	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160000	1	0	2	160002	0	44	0	5020	3	16	5	4	80040	0	160000	80000	10	80044	80044	80044	80044	80044
240024	80043	621	0	0	0	0	0	0	5	80028	16	16	1	25	240012	10	80007	160000	10	80000	160000	50	3679532	641044	0	80018	80043	80043	49978	3	50023	240010	20	160000	80000	20	320000	160000	80043	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	5	160002	2	42	0	5020	3	16	3	3	80040	0	160000	80000	10	80044	80044	80044	80044	80044
240024	80043	620	0	0	0	12	3	0	495	80028	16	16	108	25	240013	10	80000	160000	10	80000	160000	50	3679532	642160	1	80018	80040	80043	49978	3	50020	240010	20	160000	80000	20	320244	160000	80040	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	2	160002	2	44	0	5020	3	16	5	5	80040	0	160000	80000	10	80044	80044	80044	80043	80044
240024	80040	620	0	0	0	0	3	0	2	80028	16	16	1	25	240016	10	80761	160000	10	80000	160000	50	3679532	640503	0	80018	80042	80043	49978	7	50023	240010	20	160000	80000	20	320000	160000	80043	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	5020	4	16	3	4	80040	0	160000	80000	10	80041	80044	80044	80044	80044
240024	80043	621	0	0	0	0	3	0	237	80028	16	16	1	25	240015	10	80932	160000	10	80000	160000	50	3679532	641245	0	80018	80043	80043	49978	3	50023	240010	20	160000	80000	20	320244	160000	80043	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160000	0	0	2	160002	2	42	0	5020	4	16	5	4	80040	0	160000	80000	10	80044	80044	80044	80041	80044
240024	80040	621	0	0	0	12	0	0	3	80032	16	16	1	25	240021	10	80006	160000	10	80000	160000	50	3679388	640016	0	80018	80043	80043	49975	3	50023	240010	20	160000	80000	20	320000	160000	80043	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160002	1	0	2	160002	2	42	0	5020	4	16	4	4	80040	0	160000	80000	10	80044	80044	80044	80044	80041
240024	80043	620	0	0	0	144	3	0	257	80028	16	16	1	25	240013	10	80004	160000	10	80000	160000	50	3679484	642160	0	80018	80043	80043	49978	3	50023	240010	20	160122	80000	20	320000	160000	80043	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	2	160062	2	42	0	5020	3	16	4	3	80195	0	160000	80000	10	80044	80044	80044	80216	80044
240024	80043	620	0	0	0	12	3	0	1	80028	16	16	0	25	240016	10	80002	160000	10	80000	160000	50	3685940	640000	0	80018	80043	80043	49978	3	50023	240010	20	160000	80000	20	320000	160000	80040	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	0	160000	2	0	0	5020	4	25	3	4	80350	0	160000	80000	10	80044	80044	80044	80044	80044

ST1 (multiple, 3 regs, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations