Firestorm: ST1 (multiple, 3 regs, 2D) measurements

Code:

  st1 { v0.2d, v1.2d, v2.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	1e	1f	22	23	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
63005	29558	237	4	0	3	0	0	3	0	0	69	1	1	0	4587	28975	3	3	23270	3000	3000	3000	15903	9	16995	0	28309	29255	3	10	3000	3000	6000	29125	29168	1	1	61001	1000	1000	3000	0	6	0	3000	1	0	6	3000	0	6	0	0	0	12815	9019	6807	3115	1	48	20554	3033	3805	14	52	49	28413	16461	13335	15006	3000	29240	29305	29318	29277	29244
63004	29208	219	0	0	2	0	0	2	0	0	240	1	0	0	4560	29040	3	0	23168	3000	3000	3000	15901	6	17060	0	28310	29247	22	10	3000	3003	6000	29195	29089	1	1	61001	1000	1000	3000	0	0	0	3000	1	0	6	3000	0	9	0	0	0	12923	9159	6940	3107	1	45	20638	3034	3806	15	46	50	28401	16371	13395	15064	3000	29309	29247	29298	29312	29181
63004	29297	219	0	0	0	0	0	1	0	0	9	1	0	0	4552	29062	3	0	23161	3000	3000	3000	15900	5	17027	0	28324	29334	3	10	3000	3000	6000	29107	29161	1	1	61001	1000	1000	3000	0	0	0	3000	0	0	0	3000	0	6	0	0	0	13169	9347	6904	3163	1	49	20770	3153	3814	13	52	70	28555	16241	13330	14747	3000	29376	29374	29335	29329	29376
63004	29238	227	0	0	2	0	0	2	0	0	9	1	0	0	4644	29083	0	0	23284	3000	3000	3000	15895	7	17036	0	28795	29638	3	27	3000	3000	6006	29421	29360	1	1	61001	1000	1000	3000	4	0	1	3003	0	1	3	3000	5	9	3	0	0	13758	10169	7230	3401	1	48	19435	3322	3799	15	47	52	27908	14326	11817	13422	3000	28227	28180	28332	28430	28154
63004	28197	212	0	1	2	0	0	1	1	0	9	3	0	0	5060	28092	4	0	22131	3000	3000	3000	15906	8	17048	0	27974	28282	3	10	3000	3000	6000	28277	28221	1	1	61001	1000	1000	3000	0	9	0	3000	1	0	0	3000	0	9	0	0	0	13553	9966	7243	3370	0	53	19511	3319	3811	13	40	47	27888	14498	11732	13015	3000	28244	28339	28396	28334	28356
63004	28483	212	0	0	1	0	0	1	0	0	375	1	0	0	5136	28149	4	0	22137	3000	3000	3000	15907	9	17055	0	27895	28533	3	10	3000	3000	6000	28159	28366	1	1	61001	1000	1000	3000	0	0	0	3000	0	0	0	3000	0	0	0	0	0	13741	10302	7060	3526	0	47	19614	3334	3812	7	48	52	27864	14011	11802	13038	3000	28218	28164	28281	28312	28679
63004	28518	223	0	0	1	0	0	1	0	0	609	1	0	0	5076	28126	0	4	22140	3000	3000	3000	15899	4	17046	0	28055	28326	3	10	3000	3000	6000	28205	28171	1	1	61001	1000	1000	3000	0	9	0	3000	0	0	0	3001	0	6	0	0	0	13871	10187	7215	3477	1	50	19590	3300	3813	15	44	51	27873	14421	12036	13645	3000	28322	27970	28390	28311	28190
63004	28204	213	0	0	1	0	0	2	0	0	429	4	0	1	5122	28240	4	4	22119	3000	3000	3000	15902	10	17052	0	28081	28487	3	10	3000	3000	6000	28108	28267	1	1	61001	1000	1000	3000	0	0	0	3000	0	0	0	3000	0	0	0	0	0	13722	9969	7089	3314	1	50	19730	3310	3812	14	47	47	27972	14620	12004	12914	3000	28381	28181	28309	28406	28235
63004	28359	212	0	0	1	0	0	0	0	0	0	1	0	0	5011	28253	4	4	22211	3000	3000	3000	15905	9	17057	0	27893	28135	3	10	3000	3000	6000	28337	28238	1	1	61001	1000	1000	3000	0	9	0	3000	0	0	0	3000	0	9	0	0	0	13197	9535	7015	3158	0	49	20043	3178	3811	13	46	49	27990	16122	13133	14751	3000	29193	29224	29188	29247	29347
63004	29339	227	1	1	1	2	2	2	0	3	273	92	0	0	4596	28940	0	3	23087	3000	3000	3000	15908	4	17049	0	28717	29453	3	10	3000	3000	6000	29259	29184	1	1	61001	1000	1000	3000	0	6	2	3000	0	0	0	3000	3	12	0	0	0	13049	9315	6898	3144	0	50	20901	3419	3813	16	47	51	28245	15263	12503	14176	3000	28605	28727	28646	28544	28753

Count: 8

Code:

  st1 { v0.2d, v1.2d, v2.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	120191	931	0	0	0	0	0	0	12	19	0	0	0	120027	16	0	0	25	240100	100	240000	114	240007	500	5519455	0	120017	120042	120040	89961	7	90013	240225	200	240016	200	480032	120040	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	2	5	240002	2	0	0	0	1	1	1	5117	0	16	0	0	120047	0	0	240000	100	120051	120043	120043	120043	120180
240204	120042	931	0	0	0	0	0	1	264	283	0	0	0	120307	16	0	73	55	240288	113	241620	115	240432	601	5533860	0	120375	120181	120464	90239	27	90115	240217	200	240360	200	480476	120182	120603	2	1	80201	100	99	100	100	80000	80000	100	241442	0	36	692	0	241082	0	0	793	240122	2	34	0	0	0	0	0	5134	1	34	1	1	120277	19	0	240000	100	120464	120321	120043	120041	120052
240204	120042	931	0	0	0	0	0	0	12	19	0	0	0	120027	16	16	0	25	240100	100	240000	100	240000	500	5519424	0	120017	120042	120050	89955	3	90009	240100	200	240000	200	480000	120042	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	0	0	0	240002	1	0	2	240002	2	34	0	0	0	0	0	5110	1	16	1	1	120037	0	0	240000	100	120043	120123	120052	120043	120043
240204	120051	930	0	0	0	0	0	0	0	3	0	0	0	120027	16	16	0	25	240100	100	240000	100	240000	500	5519424	0	120025	120042	120051	89963	3	90000	240100	200	240000	200	480000	120042	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240000	0	0	2	240002	2	34	0	0	0	0	0	5110	1	16	1	1	120039	0	0	240000	100	120043	120043	120043	120043	120052
240204	120042	931	0	0	0	0	0	0	12	3	0	0	0	120027	16	16	0	25	240100	100	240000	100	240000	500	5519352	0	120015	120042	120050	89963	3	89998	240100	200	240000	200	480000	120042	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	8	240002	2	0	0	0	0	0	0	5110	1	16	0	1	120048	0	0	240000	100	120041	120043	120043	120043	120043
240204	120042	931	0	0	0	0	0	0	0	3	0	0	0	120027	0	16	7	25	240100	100	240000	100	240000	500	5519908	0	120033	120059	120059	89974	3	90017	240100	200	240000	200	480000	120050	120052	1	1	80201	100	99	100	100	80000	80000	100	240015	15	36	0	1	240016	0	1	22	240002	18	34	0	0	0	0	0	5110	1	16	1	1	120039	0	0	240000	100	120043	120043	120043	120043	120051
240204	120042	930	0	0	0	0	0	0	0	10	0	0	0	120035	0	16	0	25	240100	100	240000	100	240000	500	5519424	0	120026	120042	120042	89964	3	90000	240100	200	240000	200	480000	120051	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	2	240002	2	34	0	0	1	0	0	5110	1	16	1	1	120037	0	0	240000	100	120043	120041	120041	120043	120052
240204	120042	930	0	0	0	0	0	0	3	0	1	0	0	120027	16	16	0	25	240100	100	240000	100	240000	500	5519424	0	120025	120042	120128	89953	3	90000	240100	200	240000	200	480000	120050	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	2	240002	2	34	0	0	0	0	0	5110	1	16	1	1	120039	0	0	240000	100	120043	120043	120050	120043	120050
240204	120050	931	0	0	0	0	0	0	36	3	0	0	0	120027	0	16	3	25	240100	100	240000	100	240000	500	5519424	0	120024	120042	120042	89962	3	90000	240100	200	240000	200	480000	120050	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	36	0	0	240002	0	0	2	240002	2	34	0	0	0	0	0	5110	1	16	1	1	120039	0	0	240000	100	120043	120043	120051	120043	120043
240204	120050	931	0	0	0	0	0	0	12	3	1	0	0	120027	16	16	0	25	240100	100	240000	100	240000	500	5519424	0	120017	120040	120040	89953	3	90000	240100	200	240000	200	480000	120042	120049	1	1	80201	100	99	100	100	80000	80000	100	240060	0	34	0	0	240002	1	0	2	240002	2	0	0	0	0	0	0	5110	1	16	1	1	120039	0	0	240000	100	120041	120041	120043	120043	120043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	22	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	120049	931	1	0	0	0	21	5	12	0	1	0	0	120036	16	16	0	25	240010	10	240000	10	240000	50	5519424	0	120017	0	120042	120181	89984	3	90022	240010	20	240000	20	480242	120051	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240000	0	0	3	240000	2	34	0	0	0	0	5020	11	16	6	13	120039	0	240000	10	120043	120181	120041	120041	120050
240024	120051	930	0	0	0	0	0	0	12	9	0	0	0	120025	0	16	0	25	240010	10	240000	10	240000	50	5519352	0	120026	0	120051	120180	89977	3	90022	240010	20	240000	20	480000	120050	120040	1	1	80021	10	9	10	10	80000	80000	10	240060	0	34	0	0	240002	1	0	2	240002	2	34	0	0	0	0	5020	13	16	13	13	120046	0	240000	10	121441	120043	120043	120043	120043
240024	120042	931	0	0	0	0	0	0	12	3	0	0	0	120027	16	16	0	25	240010	10	240000	10	240000	50	5524260	0	120025	0	120042	120042	89977	3	90030	240010	20	240000	20	480000	120050	120040	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	5	0	812	240002	2	34	0	0	0	0	5020	6	16	6	14	120039	0	240000	10	120041	120058	120043	120043	120043
240024	120042	931	0	0	0	0	0	0	0	9	0	0	0	120027	16	16	0	25	240010	10	240000	10	240000	50	5519424	0	120017	0	120042	120042	89984	3	90022	240010	20	240000	20	480000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240014	14	36	0	2	240076	1	1	20	240002	16	42	14	0	0	0	5020	13	16	12	12	120049	1	240000	10	120059	120069	120054	120048	120053
240024	120059	930	1	1	2	0	0	0	0	19	0	0	1	120044	0	16	5	25	240010	10	240000	10	240000	50	5520268	0	120022	0	120281	120059	89984	3	90039	240010	20	240000	20	480000	120062	120052	1	1	80021	10	9	10	10	80000	80000	10	240014	14	36	0	1	240014	1	0	18	240062	14	38	14	0	0	0	5020	13	16	6	13	120165	0	240000	10	120051	120043	120043	120043	120043
240024	120042	931	0	0	0	0	0	0	3	3	0	0	0	120027	16	16	0	25	240010	10	240000	10	240000	50	5519424	0	120017	0	120042	120050	89977	3	90135	240010	20	240000	20	480000	120040	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	1	0	2	240002	0	34	0	0	0	0	5020	13	16	6	13	120039	0	240000	10	120051	120043	120043	120043	120182
240024	120040	931	0	0	0	0	3	0	0	3	0	0	0	120027	16	16	0	25	240010	10	240120	10	240000	50	5519424	0	120017	0	120040	120050	89977	3	90137	240010	20	240000	20	480000	120042	120040	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	2	240002	2	34	0	0	0	0	5020	12	16	13	13	120039	0	240000	10	120041	120043	120043	120055	120043
240024	120040	930	0	0	0	0	0	0	0	9	0	0	0	120027	16	16	0	25	240010	10	240000	10	240000	50	5524260	0	120025	0	120042	120042	89977	3	90022	240010	20	240000	20	480000	120040	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	8	240002	2	34	0	0	0	0	5020	14	16	13	13	120047	0	240000	10	120044	120050	120043	120043	120041
240024	120042	931	0	0	0	0	0	0	12	3	0	0	0	120167	16	16	76	25	240010	10	240000	10	240000	50	5520000	0	120017	6	120042	120050	90070	3	90022	240010	20	240000	20	480000	120042	120040	1	1	80021	10	9	10	10	80000	80000	10	240000	2	0	0	0	240002	1	0	2	240002	2	34	0	0	0	0	5020	13	16	13	13	120039	0	240000	10	120043	120043	120055	120043	120050
240024	120042	930	0	0	0	0	0	0	0	3	0	0	0	120027	16	16	0	25	240010	10	240000	10	240000	50	5519424	0	120026	0	120042	120040	89977	3	90022	240010	20	240000	20	480000	120050	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	1	0	0	240002	2	34	0	0	0	0	5020	11	16	8	14	120160	2	240000	10	120462	120182	120329	120337	120462

ST1 (multiple, 3 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations