Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st1 { v0.2s, v1.2s, v2.2s }, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 60 nops): 3.000
Issues: 3.000
Integer unit issues: 0.000
Load/store unit issues: 2.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 24 | 3a | 3f | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5e | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | l1d cache miss st nonspec (c0) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
63006 | 29479 | 236 | 4 | 4 | 0 | 1 | 3 | 0 | 0 | 0 | 6 | 1 | 0 | 4618 | 29222 | 18428 | 3000 | 1000 | 2000 | 1000 | 2000 | 15907 | 8000 | 0 | 10 | 21777 | 29229 | 29567 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29356 | 29299 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 105 | 13325 | 9118 | 6947 | 3217 | 0 | 73 | 20869 | 3217 | 3819 | 19 | 72 | 73 | 28774 | 16101 | 13478 | 14882 | 2000 | 1000 | 29352 | 29452 | 29456 | 29542 | 29456 |
63004 | 29508 | 237 | 0 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 89 | 0 | 4706 | 29301 | 18390 | 3000 | 1000 | 2000 | 1000 | 2000 | 15904 | 8000 | 0 | 2 | 21766 | 29165 | 29471 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29451 | 29389 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 438 | 2000 | 4 | 2 | 93 | 13342 | 9288 | 6912 | 3161 | 0 | 75 | 20987 | 3302 | 3819 | 22 | 74 | 74 | 28705 | 16240 | 13405 | 14772 | 2000 | 1000 | 29427 | 29575 | 29446 | 29375 | 29519 |
63004 | 29517 | 237 | 0 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | 162 | 0 | 0 | 4647 | 29261 | 18502 | 3000 | 1000 | 2000 | 1000 | 2000 | 15908 | 8000 | 0 | 2 | 21758 | 29097 | 29510 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29394 | 29412 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13263 | 9379 | 7004 | 3116 | 0 | 66 | 20820 | 3265 | 3816 | 25 | 71 | 65 | 28691 | 16392 | 13351 | 15052 | 2000 | 1000 | 29476 | 29622 | 29667 | 29583 | 29350 |
63004 | 29382 | 238 | 0 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | 4670 | 29317 | 18488 | 3000 | 1000 | 2000 | 1000 | 2000 | 15913 | 8000 | 0 | 1 | 21816 | 29146 | 29484 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29354 | 29362 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13273 | 9428 | 7018 | 3110 | 1 | 69 | 20801 | 3318 | 3822 | 8 | 70 | 63 | 28748 | 16174 | 13163 | 15049 | 2000 | 1000 | 29447 | 29518 | 29348 | 29500 | 29461 |
63004 | 29411 | 236 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 4731 | 29334 | 18370 | 3000 | 1000 | 2000 | 1000 | 2000 | 15902 | 8000 | 0 | 2 | 21740 | 29174 | 29506 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29467 | 29359 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13308 | 9385 | 6951 | 3151 | 1 | 70 | 20787 | 3149 | 3818 | 16 | 63 | 75 | 28695 | 16190 | 13433 | 15147 | 2000 | 1000 | 29360 | 29579 | 29432 | 29473 | 29473 |
63004 | 29506 | 237 | 0 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | 4587 | 29352 | 18519 | 3000 | 1000 | 2000 | 1000 | 2000 | 15905 | 8000 | 0 | 1 | 21741 | 29453 | 29718 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29481 | 29422 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13315 | 9323 | 6882 | 3153 | 0 | 72 | 20795 | 3335 | 3824 | 17 | 69 | 72 | 28847 | 16122 | 13259 | 15047 | 2000 | 1000 | 29446 | 29561 | 29483 | 29403 | 29504 |
63004 | 29487 | 236 | 0 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 4722 | 29280 | 18585 | 3000 | 1000 | 2000 | 1000 | 2000 | 15978 | 8000 | 0 | 3 | 21786 | 29153 | 29439 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29469 | 29518 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 3 | 2000 | 4 | 0 | 0 | 13320 | 9457 | 6914 | 3146 | 0 | 69 | 20779 | 3196 | 3815 | 14 | 69 | 72 | 28794 | 16195 | 13246 | 14980 | 2000 | 1000 | 29557 | 29529 | 29563 | 29421 | 29532 |
63004 | 29499 | 237 | 0 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | 6 | 1 | 0 | 4704 | 29321 | 18277 | 3000 | 1000 | 2000 | 1000 | 2000 | 15903 | 8000 | 0 | 2 | 21720 | 29245 | 29569 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29401 | 29384 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13190 | 9416 | 6925 | 3122 | 0 | 66 | 20817 | 3282 | 3818 | 12 | 73 | 67 | 28830 | 16210 | 13333 | 15275 | 2000 | 1000 | 29447 | 29394 | 29501 | 29592 | 29429 |
63004 | 29409 | 237 | 0 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | 132 | 1 | 0 | 4733 | 29292 | 18484 | 3000 | 1000 | 2000 | 1000 | 2000 | 15905 | 8000 | 0 | 0 | 21796 | 29113 | 29469 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29466 | 29419 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13197 | 9572 | 6920 | 3136 | 0 | 72 | 20805 | 3308 | 3816 | 23 | 73 | 66 | 28806 | 16270 | 13418 | 15159 | 2000 | 1000 | 29520 | 29509 | 29499 | 29555 | 29454 |
63004 | 29498 | 238 | 0 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | 12 | 1 | 0 | 4656 | 29198 | 18503 | 3000 | 1000 | 2000 | 1000 | 2000 | 15905 | 8000 | 0 | 1 | 21819 | 29238 | 29387 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29332 | 29448 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 2 | 0 | 2000 | 4 | 0 | 0 | 13184 | 9241 | 6965 | 3133 | 0 | 72 | 20891 | 3238 | 3814 | 18 | 74 | 66 | 28765 | 16080 | 13414 | 15060 | 2000 | 1000 | 29525 | 29479 | 29508 | 29550 | 29488 |
Count: 8
Code:
st1 { v0.2s, v1.2s, v2.2s }, [x6] st1 { v0.2s, v1.2s, v2.2s }, [x6] st1 { v0.2s, v1.2s, v2.2s }, [x6] st1 { v0.2s, v1.2s, v2.2s }, [x6] st1 { v0.2s, v1.2s, v2.2s }, [x6] st1 { v0.2s, v1.2s, v2.2s }, [x6] st1 { v0.2s, v1.2s, v2.2s }, [x6] st1 { v0.2s, v1.2s, v2.2s }, [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
240206 | 80047 | 643 | 1 | 1 | 0 | 0 | 0 | 3 | 18 | 1 | 0 | 42 | 1 | 80038 | 16 | 0 | 4 | 25 | 240123 | 100 | 80046 | 160000 | 100 | 80006 | 160006 | 500 | 3680022 | 640171 | 80027 | 80058 | 80061 | 49976 | 6 | 50004 | 240112 | 200 | 160016 | 80008 | 200 | 320032 | 160016 | 80058 | 80058 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 15 | 38 | 1 | 0 | 160014 | 1 | 0 | 19 | 160002 | 16 | 36 | 14 | 1 | 1 | 1 | 1 | 5116 | 0 | 16 | 0 | 0 | 80039 | 160000 | 80000 | 100 | 80055 | 80043 | 80043 | 80041 | 80043 |
240204 | 80042 | 643 | 0 | 0 | 0 | 0 | 0 | 3 | 3 | 0 | 0 | 51 | 0 | 80027 | 16 | 16 | 0 | 25 | 240151 | 100 | 81046 | 160000 | 100 | 80006 | 160007 | 500 | 3679491 | 642333 | 80017 | 80042 | 80042 | 49960 | 6 | 50003 | 240113 | 200 | 160016 | 80008 | 200 | 320032 | 160016 | 80040 | 80042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 34 | 0 | 0 | 1 | 1 | 1 | 5116 | 0 | 16 | 0 | 0 | 80039 | 160000 | 80000 | 100 | 80043 | 80043 | 80043 | 80051 | 80043 |
240204 | 80042 | 642 | 0 | 0 | 0 | 0 | 0 | 114 | 3 | 1 | 0 | 37 | 0 | 80027 | 0 | 0 | 0 | 25 | 240108 | 100 | 80517 | 160000 | 100 | 80000 | 160000 | 500 | 3679388 | 643529 | 80017 | 80042 | 80040 | 49955 | 3 | 49998 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80040 | 80042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 5 | 160002 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | 5151 | 1 | 16 | 1 | 1 | 80047 | 160000 | 80000 | 100 | 80043 | 80050 | 80043 | 80043 | 80051 |
240204 | 80049 | 643 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 528 | 0 | 80027 | 16 | 0 | 0 | 25 | 240836 | 100 | 81092 | 160000 | 100 | 80000 | 160000 | 500 | 3679388 | 643339 | 80017 | 80042 | 80042 | 49955 | 3 | 50000 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80042 | 80042 | 1 | 1 | 80202 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 34 | 0 | 0 | 160002 | 2 | 0 | 5 | 160002 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 160000 | 80000 | 100 | 80043 | 80043 | 80043 | 80043 | 80043 |
240204 | 80042 | 643 | 0 | 0 | 0 | 0 | 0 | 6 | 3 | 0 | 0 | 725 | 0 | 80027 | 16 | 16 | 0 | 25 | 240836 | 100 | 80684 | 160000 | 100 | 80000 | 160000 | 500 | 3679868 | 640138 | 80025 | 80042 | 80042 | 49953 | 3 | 49998 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80040 | 80049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 0 | 0 | 0 | 160000 | 0 | 0 | 0 | 160002 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80039 | 160000 | 80000 | 100 | 80041 | 80043 | 80051 | 80043 | 80043 |
240204 | 80042 | 642 | 0 | 0 | 0 | 0 | 0 | 3 | 3 | 0 | 0 | 872 | 0 | 80027 | 16 | 16 | 0 | 25 | 240498 | 100 | 80000 | 160000 | 100 | 80000 | 160000 | 500 | 3679388 | 640109 | 80017 | 80042 | 80042 | 49953 | 3 | 50007 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80042 | 80042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80047 | 160000 | 80000 | 100 | 80043 | 80041 | 80043 | 80043 | 80043 |
240204 | 80040 | 642 | 0 | 0 | 0 | 0 | 0 | 3 | 9 | 0 | 0 | 693 | 0 | 80027 | 0 | 16 | 0 | 25 | 240638 | 100 | 80777 | 160000 | 100 | 80000 | 160000 | 500 | 3679460 | 642635 | 80017 | 80049 | 80042 | 49955 | 3 | 50009 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80042 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 34 | 0 | 0 | 160000 | 0 | 0 | 2 | 160002 | 2 | 36 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80046 | 160000 | 80000 | 100 | 80043 | 80043 | 80051 | 80043 | 80043 |
240204 | 80042 | 642 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1433 | 0 | 80025 | 0 | 16 | 0 | 25 | 240966 | 100 | 80536 | 160000 | 100 | 80000 | 160000 | 500 | 3679460 | 642621 | 80017 | 80042 | 80042 | 49962 | 3 | 50000 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80042 | 80042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 34 | 0 | 0 | 160002 | 2 | 0 | 14 | 160002 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80202 | 160000 | 80000 | 100 | 80043 | 80052 | 80041 | 80043 | 80050 |
240204 | 80050 | 643 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 975 | 1 | 80038 | 16 | 0 | 6 | 25 | 240126 | 100 | 80554 | 160000 | 100 | 80000 | 160000 | 500 | 3680231 | 642496 | 80025 | 80042 | 80042 | 49955 | 3 | 50000 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80049 | 80050 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 8 | 160002 | 16 | 36 | 14 | 1 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80049 | 160000 | 80000 | 100 | 80043 | 80043 | 80043 | 80051 | 80043 |
240204 | 80040 | 643 | 0 | 0 | 0 | 0 | 0 | 3 | 14 | 1 | 0 | 52 | 1 | 80035 | 16 | 0 | 9 | 25 | 240122 | 100 | 80032 | 160000 | 100 | 80000 | 160000 | 500 | 3680255 | 640134 | 80017 | 80042 | 80042 | 49963 | 3 | 50000 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80042 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 34 | 0 | 0 | 160002 | 2 | 0 | 8 | 160002 | 16 | 36 | 14 | 1 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80056 | 160000 | 80000 | 100 | 80051 | 80048 | 80049 | 80053 | 80059 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
240026 | 80049 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 0 | 889 | 0 | 80035 | 16 | 16 | 0 | 25 | 240880 | 10 | 80979 | 160000 | 10 | 80000 | 160000 | 50 | 3686468 | 640020 | 1 | 80017 | 80040 | 80042 | 49975 | 3 | 50032 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80042 | 80042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 1 | 0 | 2 | 160002 | 2 | 34 | 0 | 0 | 5020 | 13 | 26 | 8 | 12 | 80047 | 0 | 160000 | 80000 | 10 | 80043 | 80043 | 80060 | 80043 | 80043 |
240024 | 80042 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 132 | 3 | 0 | 1002 | 0 | 80035 | 0 | 0 | 2 | 25 | 241035 | 10 | 80872 | 160000 | 10 | 80000 | 160000 | 50 | 3679460 | 643400 | 1 | 80017 | 80040 | 80050 | 49977 | 3 | 50022 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80051 | 80050 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 8 | 160002 | 2 | 34 | 0 | 0 | 5020 | 14 | 16 | 6 | 14 | 80048 | 0 | 160000 | 80000 | 10 | 80044 | 80043 | 80043 | 80053 | 80043 |
240024 | 80042 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 836 | 0 | 80025 | 0 | 16 | 0 | 25 | 240754 | 10 | 80522 | 160000 | 10 | 80000 | 160000 | 50 | 3679460 | 640012 | 1 | 80017 | 80050 | 80050 | 49975 | 3 | 50022 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80050 | 80050 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 1 | 0 | 5 | 160002 | 2 | 36 | 0 | 0 | 5020 | 7 | 16 | 18 | 8 | 80039 | 0 | 160000 | 80000 | 10 | 80043 | 80052 | 80051 | 80043 | 80043 |
240024 | 80042 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 995 | 0 | 80036 | 16 | 0 | 0 | 25 | 241055 | 10 | 80615 | 160000 | 10 | 80000 | 160000 | 50 | 3679460 | 640023 | 1 | 80017 | 80042 | 80042 | 49977 | 3 | 50022 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80042 | 80042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 2 | 0 | 8 | 160002 | 2 | 34 | 0 | 0 | 5020 | 7 | 16 | 13 | 11 | 80047 | 0 | 160000 | 80000 | 10 | 80041 | 80043 | 80041 | 80044 | 80051 |
240024 | 80050 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 711 | 0 | 80027 | 16 | 16 | 0 | 25 | 240677 | 10 | 80999 | 160000 | 10 | 80000 | 160000 | 50 | 3679460 | 640023 | 1 | 80017 | 80042 | 80042 | 49977 | 3 | 50031 | 240010 | 20 | 160000 | 80122 | 20 | 320732 | 160368 | 80548 | 80544 | 5 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160180 | 2 | 34 | 257 | 3 | 160242 | 1 | 2 | 3982 | 160242 | 2 | 34 | 0 | 0 | 5063 | 6 | 43 | 13 | 14 | 80626 | 0 | 160000 | 80000 | 10 | 80044 | 80050 | 80043 | 80052 | 80043 |
240024 | 80042 | 620 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 3 | 0 | 1055 | 0 | 80027 | 16 | 16 | 0 | 25 | 241027 | 10 | 80533 | 160000 | 10 | 80000 | 160000 | 50 | 3679460 | 641026 | 1 | 80017 | 80049 | 80049 | 49977 | 3 | 50022 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80042 | 80214 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 34 | 0 | 1 | 5020 | 13 | 16 | 7 | 16 | 80046 | 0 | 160000 | 80000 | 10 | 80043 | 80043 | 80043 | 80052 | 80043 |
240024 | 80042 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 615 | 0 | 80027 | 16 | 16 | 0 | 25 | 240709 | 10 | 80736 | 160000 | 10 | 80000 | 160000 | 50 | 3679460 | 642519 | 1 | 80025 | 80042 | 80042 | 50098 | 3 | 50022 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80042 | 80042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 34 | 0 | 0 | 5020 | 7 | 16 | 14 | 8 | 80039 | 0 | 160000 | 80000 | 10 | 80050 | 80043 | 80043 | 80043 | 80052 |
240024 | 80051 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 91 | 0 | 618 | 0 | 80027 | 16 | 16 | 106 | 25 | 241022 | 10 | 80963 | 160000 | 10 | 80000 | 160000 | 50 | 3679460 | 642580 | 1 | 80015 | 80042 | 80042 | 49977 | 3 | 50022 | 240010 | 20 | 160000 | 80062 | 20 | 320000 | 160000 | 80042 | 80042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 1 | 0 | 8 | 160000 | 2 | 0 | 0 | 0 | 5020 | 14 | 16 | 13 | 13 | 80047 | 0 | 160000 | 80000 | 10 | 80216 | 80043 | 80043 | 80050 | 80043 |
240024 | 80042 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 926 | 0 | 80027 | 16 | 16 | 0 | 25 | 241012 | 10 | 80589 | 160000 | 10 | 80000 | 160000 | 50 | 3679460 | 642640 | 1 | 80017 | 80040 | 80050 | 49975 | 3 | 50022 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80050 | 80050 | 2 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 0 | 255 | 0 | 160002 | 1 | 0 | 2 | 160002 | 2 | 34 | 0 | 0 | 5020 | 11 | 16 | 7 | 15 | 80048 | 0 | 160000 | 80000 | 10 | 80043 | 80043 | 80043 | 80043 | 80052 |
240024 | 80051 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 882 | 0 | 80034 | 16 | 16 | 2 | 25 | 240706 | 10 | 80046 | 160000 | 10 | 80000 | 160000 | 55 | 3679460 | 642515 | 1 | 80017 | 80051 | 80050 | 49977 | 3 | 50022 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80050 | 80050 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160062 | 0 | 36 | 3 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 34 | 0 | 0 | 5020 | 13 | 16 | 11 | 13 | 80039 | 0 | 160000 | 80000 | 10 | 80043 | 80052 | 80061 | 80043 | 80043 |