Firestorm: ST1 (multiple, 3 regs, 4H) measurements

Code:

  st1 { v0.4h, v1.4h, v2.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63006	29513	236	4	0	3	0	0	2	0	0	0	0	0	1	0	0	4638	29126	2	0	18540	3000	1000	2000	1000	2000	15909	8000	18	0	0	21668	29179	29499	3	10	3000	2000	1000	4000	2000	29337	29335	1	1	61001	1000	1000	2003	3	8	1	2002	0	1	8	2000	2	0	2	0	0	13235	9324	6897	3156	0	51	20769	3380	3800	21	47	41	28747	16445	13250	14981	2000	1000	29508	29372	29408	29507	29426
63004	29377	237	0	1	1	0	0	1	0	0	0	12	1	0	0	0	4670	29207	2	2	18585	3000	1000	2000	1000	2000	15902	8000	18	0	0	21714	29126	29493	3	10	3000	2000	1000	4000	2000	29414	29277	1	1	61001	1000	1000	2003	0	4	1	2002	0	1	2	2000	2	0	0	0	0	13221	9375	6932	3183	0	41	20769	3209	3807	22	50	45	28825	16216	13363	15090	2000	1000	29397	29468	29465	29417	29581
63004	29410	236	0	1	0	0	0	1	0	0	0	21	2	0	0	0	4726	29266	2	2	18549	3000	1000	2000	1000	2000	15904	8000	12	0	0	21731	29158	29529	3	10	3000	2000	1000	4000	2000	29222	29423	1	1	61001	1000	1000	2000	0	6	2	2002	1	2	0	2000	0	0	0	0	0	13293	9478	6953	3137	1	43	20806	3384	3808	22	46	43	28713	16324	13422	15103	2000	1000	29374	29306	29520	29435	29391
63004	29409	237	0	0	1	0	0	1	0	0	0	0	1	0	0	0	4622	29217	2	2	18471	3000	1000	2000	1000	2000	15907	8000	12	0	0	21706	29194	29358	3	10	3000	2000	1000	4000	2000	29377	29311	1	1	61001	1000	1000	2004	0	6	1	2002	0	1	2	2000	0	0	0	0	0	13232	9406	6896	3188	0	52	20779	3265	3814	25	48	49	28708	16046	13340	15199	2000	1000	29499	29459	29443	29379	29598
63004	29392	237	0	0	0	0	0	0	0	0	0	0	1	0	0	0	4679	29240	0	0	18515	3000	1000	2000	1000	2000	15905	8000	7	0	0	21774	29080	29488	3	10	3000	2000	1000	4000	2000	29435	29405	1	1	61001	1000	1000	2000	0	4	0	2002	0	1	0	2000	2	0	2	0	0	13029	9275	6888	3118	1	48	20828	3239	3812	21	48	48	28773	16121	13369	15359	2000	1000	29549	29464	29458	29583	29392
63004	29469	238	0	1	0	0	0	0	0	0	0	0	3	0	0	0	4603	29365	0	0	18483	3000	1000	2000	1000	2000	15903	8000	7	0	0	21750	29177	29478	3	10	3000	2000	1000	4000	2000	29498	29487	1	1	61001	1000	1000	2002	0	0	1	2002	0	1	2	2000	0	4	0	0	0	13037	9390	7002	3120	0	47	20771	3293	3813	29	48	37	28764	16400	13268	14936	2000	1000	29536	29383	29380	29499	29504
63004	29402	237	0	0	0	0	0	1	0	0	0	0	3	0	0	0	4541	29238	0	0	18539	3000	1000	2000	1000	2000	15908	8000	5	0	0	21520	29083	29378	3	10	3000	2000	1000	4000	2000	29357	29289	1	1	61001	1000	1000	2003	3	8	2	2002	0	1	2	2000	0	6	0	0	0	13065	9271	6891	3181	0	49	20758	3302	3805	24	48	49	28688	15940	13510	14913	2000	1000	29498	29402	29442	29470	29593
63004	29395	237	0	0	1	0	0	0	1	0	0	0	1	1	0	0	4647	29297	0	2	18547	3000	1000	2000	1000	2000	15913	8000	5	0	0	21740	29105	29398	3	10	3000	2000	1000	4000	2000	29437	29488	1	1	61001	1000	1000	2003	0	6	1	2002	0	1	5	2000	0	4	0	0	358	13208	9294	6910	3102	0	46	20796	3227	3813	21	48	45	28675	16219	13514	14958	2000	1000	29566	29458	29421	29375	29451
63004	29579	235	0	0	1	0	0	1	0	0	0	0	1	0	0	0	4656	29276	0	0	18403	3000	1000	2000	1000	2000	15902	8000	8	0	0	21732	29223	29516	3	10	3000	2000	1000	4000	2000	29367	29397	1	1	61001	1000	1000	2000	0	0	1	2003	0	2	0	2000	0	6	0	0	0	13088	9348	6896	3167	1	42	20941	3254	3812	19	46	47	28711	16228	13373	14853	2000	1000	29461	29436	29486	29513	29531
63004	29470	237	0	0	0	0	0	1	0	0	0	0	5	0	0	0	4641	29316	0	0	18470	3000	1000	2000	1000	2000	15906	8000	10	0	0	21742	29191	29444	3	10	3000	2000	1000	4000	2002	29399	29472	1	1	61001	1000	1000	2004	4	0	0	2002	0	2	2	2000	0	0	0	0	0	13216	9368	6863	3105	1	53	20900	3297	3812	20	45	43	28781	16357	13485	14830	2000	1000	29483	29500	29533	29476	29531

Count: 8

Code:

  st1 { v0.4h, v1.4h, v2.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	23	37	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240206	80043	600	0	0	0	0	0	0	3	0	56	80025	16	16	1	25	240785	100	80662	160000	100	80000	160000	500	3679508	640220	0	80015	0	80043	80043	49956	3	50001	240100	200	160000	80000	200	320000	160000	80043	80043	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	1	0	2	160002	0	42	0	0	5110	1	16	1	1	80040	0	160000	80000	100	80044	80044	80044	80044	80044
240204	80043	600	0	0	0	0	0	18	3	0	35	80028	16	16	1	25	240647	100	80034	160000	100	80000	160000	500	3679532	640133	0	80018	0	80043	80043	49956	3	49998	240100	200	160000	80000	200	320000	160000	80043	80043	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	6	160002	2	0	0	0	5110	1	16	1	1	80040	0	160000	80000	100	80044	80044	80041	80041	80044
240204	80043	621	0	0	0	0	0	0	3	0	926	80028	16	16	0	25	240138	100	80042	160000	100	80000	160000	500	3679508	640220	0	80018	0	80043	80040	49956	3	49998	240100	200	160000	80000	200	320000	160000	80040	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	2	160000	2	42	0	0	5110	1	16	1	1	80037	0	160000	80000	100	80044	80044	80044	80044	80044
240204	80043	621	0	0	0	0	0	0	3	0	1044	80028	16	16	1	25	240150	100	80028	160000	100	80000	160000	500	3679532	640127	0	80031	0	80043	80043	49956	3	50001	240100	200	160000	80000	200	320000	160000	80043	80043	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	5	160002	2	42	0	0	5110	1	16	1	1	80040	0	160000	80000	100	80046	80044	80044	80044	80044
240204	80043	620	0	0	0	0	0	0	3	0	48	80028	16	16	1	25	240576	100	80476	160000	100	80000	160000	500	3679532	642580	0	80018	0	80043	80043	49956	3	50001	240100	200	160000	80000	200	320000	160000	80043	80043	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	0	5110	1	16	1	1	80040	0	160000	80000	100	80044	80044	80044	80044	80044
240204	80043	620	0	0	0	0	0	0	3	0	24	80028	16	16	1	25	240130	100	80038	160000	100	80000	160000	500	3679508	640160	0	80018	0	80043	80043	49956	3	50001	240100	200	160000	80062	200	320000	160000	80043	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	0	44	0	0	160002	0	0	2	160002	0	0	2	0	5110	1	16	1	1	80037	0	160000	80000	100	80044	80044	80044	80044	80044
240204	80040	620	0	0	0	0	0	6	3	0	716	80028	16	0	1	25	240129	100	80388	160000	100	80000	160000	500	3679388	641299	0	80018	0	80043	80043	49956	3	50001	240100	200	161345	81910	202	320000	160000	80043	80043	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	5	160002	2	42	0	0	5110	1	16	1	1	80040	0	160000	80000	100	80211	80047	80044	80041	80044
240204	80040	620	0	0	0	0	0	12	3	0	42	80197	16	16	0	25	240126	100	81044	160000	100	80059	160000	500	3679532	643888	0	80018	0	80043	80213	49956	3	50001	240100	200	160000	80000	200	320000	160000	80043	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	0	5123	1	16	1	1	80040	0	160000	80000	100	80044	80044	80044	80044	80044
240204	80043	620	0	0	0	0	0	0	4	0	996	80028	16	0	1	25	240147	100	80919	160000	104	80000	160000	500	3679532	640261	0	80018	0	80043	80043	49956	3	50001	240100	200	160000	80000	200	320000	160000	80043	80043	1	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	0	160002	1	0	2	160002	2	42	0	0	5110	1	16	1	1	80037	0	160000	80000	100	80044	80044	80044	80044	80044
240204	80043	621	0	0	0	0	0	0	91	0	1021	80025	16	16	1	25	240712	100	80037	160000	100	80000	160000	500	3679532	643021	0	80018	0	80043	80040	49953	3	50000	240100	200	160123	80000	200	320000	160000	80043	80043	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160000	0	0	3	160000	2	0	0	0	5110	1	16	1	1	80040	0	160000	80000	100	80213	80041	80044	80041	80044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	22	23	37	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240026	80042	621	0	0	0	0	0	0	3	0	0	665	80207	16	16	0	25	241022	10	80699	160000	10	80000	160000	50	3686420	640011	0	80025	80042	80043	49977	3	50030	240010	20	160000	80000	20	320000	160000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	5	160000	2	34	0	0	5020	0	8	16	8	7	80039	0	0	160000	80000	10	80043	80043	80051	80043	80043
240024	80042	620	0	0	0	0	0	0	3	0	0	922	80027	16	16	0	25	240836	10	80788	160060	10	80000	160000	50	3679868	640021	0	80026	80214	80042	49977	3	50022	240010	20	160000	80000	20	320000	160000	80050	80050	1	1	80021	10	9	10	10	80000	80000	10	160060	0	34	0	0	160002	1	0	2	160002	2	34	0	0	5020	0	7	16	8	7	80039	0	0	160000	80000	10	80050	80043	80043	80052	80043
240024	80042	621	0	0	0	0	0	0	9	0	0	560	80027	0	16	0	25	240699	10	80836	160000	10	80000	160000	50	3679460	642562	0	80017	80042	80042	49984	3	50030	240010	20	160000	80000	20	320000	160000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	5	160002	2	34	0	1	5020	0	8	16	8	8	80039	0	0	160000	80000	10	80043	80043	80050	80043	80043
240024	80042	620	0	0	0	0	0	0	3	1	0	671	80027	16	16	0	25	241062	10	80633	160000	10	80000	160000	50	3679460	643180	0	80017	80042	80042	49977	3	50030	240010	20	160000	80000	20	320000	160000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	5	160002	2	34	0	0	5020	0	9	16	8	7	80039	0	0	160000	80000	10	80043	80043	80050	80043	80043
240024	80040	620	0	0	0	0	0	0	91	0	0	4	80036	16	16	0	25	240184	10	81012	160000	10	80000	160000	50	3679460	642080	0	80017	80042	80050	49977	3	50030	240010	20	160000	80000	20	320000	160124	80042	80040	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	2	160002	2	34	0	0	5020	0	8	16	7	8	80037	0	0	160000	80000	10	80051	80043	80043	80041	80041
240024	80048	620	0	0	0	0	0	0	3	0	0	559	80027	0	16	4	25	240880	10	80659	160000	10	80000	160000	50	3679388	642435	0	80017	80042	80042	49985	7	50022	240010	20	160000	80000	20	320000	160000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	5	160002	2	34	0	0	5020	0	7	16	8	7	80037	0	0	160000	80000	10	80051	80043	80043	80050	80043
240024	80042	621	1	0	0	0	0	27	3	0	0	730	80027	16	16	0	25	240742	10	80999	160000	10	80000	160000	50	3679460	642540	1	80024	80042	80042	49977	3	50022	240010	20	160000	80000	20	320000	160000	80217	80051	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	1	0	2	160002	2	34	0	0	5020	0	8	16	9	8	80039	0	0	160000	80000	10	80050	80043	80043	80043	80214
240024	80042	620	0	0	0	0	0	0	0	0	0	504	80027	16	16	0	25	240677	10	80667	160000	10	80000	160000	50	3679460	642441	0	80017	80042	80042	49985	8	50022	240010	20	160000	80000	20	320000	160000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160062	1	0	2	160002	2	34	4	0	5020	0	7	16	8	7	80047	0	0	160000	80000	10	80214	80043	80041	80041	80043
240024	80042	620	0	0	0	0	0	0	6	0	0	1014	80027	16	16	0	25	240012	10	80110	160000	10	80000	160108	50	3679460	640012	0	80017	80042	80042	50107	3	50022	240010	20	160000	80000	20	320000	160000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	2	34	0	0	160002	0	0	5	160000	2	34	0	0	5020	0	8	16	8	7	80039	0	0	160000	80000	10	80043	80043	80043	80051	80041
240024	80042	622	0	0	0	0	0	0	9	0	0	1013	80027	16	16	0	25	240892	10	81461	160000	10	80000	160000	50	3679868	640015	0	80026	80042	80042	49977	3	50022	240010	20	160000	80000	20	320000	160000	80049	80050	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	2	160002	2	34	0	0	5020	0	8	16	8	7	80039	0	0	160000	80000	10	80210	80043	80043	80050	80043

ST1 (multiple, 3 regs, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations