Firestorm: ST1 (multiple, 3 regs, 4S) measurements

Code:

  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
63005	29482	235	3	1	4	1	2	3	1	0	0	4	1	0	0	4619	29075	0	3	23297	3000	3000	3000	15898	6	1	0	17026	28583	29357	3	10	3000	3000	6000	29290	29174	1	1	61001	1000	1000	3004	4	6	0	3003	0	1	87	3000	0	9	0	0	0	13194	9710	6948	3146	0	37	20597	3239	3818	8	44	41	28699	16363	13105	14697	3000	29309	29375	29420	29351	29356
63004	29340	236	0	0	3	0	0	0	0	0	0	1	0	0	0	4641	29144	0	0	23095	3000	3003	3000	15900	0	0	0	17052	28521	29343	3	10	3000	3000	6000	29147	29086	2	1	61001	1000	1000	3000	0	0	0	3000	0	0	102	3000	0	9	0	0	0	13034	9188	7026	3147	1	33	20667	3244	3812	11	34	34	28542	16128	13126	14753	3000	29338	29236	29383	29230	29273
63004	29387	226	0	0	1	0	0	2	0	0	0	1	0	0	0	4656	29225	3	3	23150	3000	3000	3000	15904	6	0	0	17058	28576	29330	3	10	3000	3000	6000	29095	29118	1	1	61001	1000	1000	3000	0	9	0	3000	0	0	482	3000	0	9	0	0	0	13191	9397	6940	3178	1	46	20576	3228	3813	15	33	32	28497	16132	13046	14622	3000	29250	29290	29341	29182	29378
63004	29296	227	0	0	1	0	1	0	0	0	9	177	0	0	0	4633	29048	3	3	23099	3000	3000	3000	15903	6	0	0	17024	28630	29396	3	30	3000	3000	6000	29201	29194	1	1	61001	1000	1000	3000	0	9	0	3000	0	0	120	3000	0	9	0	0	0	13216	9469	6924	3194	0	41	20629	3185	3813	12	36	42	28439	16316	13272	14621	3000	29218	29393	29377	29251	29350
63004	29308	226	0	0	1	0	1	2	0	0	0	1	0	0	0	4514	29171	3	3	23076	3000	3000	3000	15941	7	0	0	17034	28620	29351	3	28	3000	3000	6000	29110	29155	1	1	61001	1000	1000	3000	0	9	0	3000	0	0	0	3000	0	9	0	0	0	13031	9357	6917	3201	1	34	20687	3251	3813	9	34	35	28543	16301	12969	14571	3000	29272	29311	29344	29293	29276
63004	29208	227	0	0	1	0	0	3	0	1	0	1	0	0	0	4664	29070	3	0	23151	3000	3000	3000	15903	6	0	0	17037	28594	29247	3	10	3000	3000	6000	29162	29131	2	1	61002	1000	1000	3000	0	9	0	3000	0	0	105	3000	0	9	0	0	0	13299	9605	6965	3140	1	38	20693	3256	3810	9	36	36	28517	16354	13113	14595	3000	29258	29225	29285	29301	29203
63004	29290	226	0	0	3	0	0	3	0	0	0	1	1	0	0	4709	29045	3	3	23166	3000	3000	3000	15904	6	0	0	17023	28557	29170	3	10	3000	3000	6000	29134	29208	1	1	61001	1000	1000	3000	0	9	0	3000	0	0	102	3000	0	9	0	0	207	13308	9381	7001	3116	1	34	20670	3129	3811	7	33	39	28503	16010	13221	14543	3000	29392	29228	29139	29130	29229
63004	29380	228	0	0	2	0	0	2	0	0	0	1	0	0	0	4647	29030	0	1	23164	3000	3000	3000	15907	1	0	0	17055	28474	29363	3	10	3000	3000	6000	29140	29059	1	1	61001	1000	1000	3000	0	6	0	3000	0	0	15	3000	0	6	0	0	0	13184	9404	6939	3254	0	38	20670	3242	3820	7	40	42	28462	16226	12810	14581	3000	29285	29316	29327	29249	29325
63004	29360	227	0	0	4	0	0	2	0	0	0	1	0	0	0	4707	29119	3	1	23228	3000	3000	3000	15899	7	0	0	17039	28389	29243	3	10	3000	3000	6000	29054	29272	1	1	61001	1000	1000	3000	0	9	0	3000	0	0	120	3000	0	9	0	0	0	13144	9349	6944	3131	2	37	20664	3208	3814	9	40	33	28621	16277	13073	14657	3000	29266	29241	29217	29313	29215
63004	29296	227	0	0	2	0	0	2	0	0	0	1	1	0	0	4672	29110	0	0	23179	3000	3000	3000	15934	6	0	0	17040	28661	29245	3	10	3000	3000	6000	29200	29035	1	1	61001	1000	1000	3000	0	9	0	3000	0	0	6	3000	0	9	0	0	0	13014	9460	6938	3187	1	43	20619	3072	3812	8	36	41	28421	16189	13182	14567	3000	29330	29238	29322	29221	29307

Count: 8

Code:

  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	120060	931	0	0	0	0	1	0	3	0	0	120027	16	16	0	25	240100	100	240000	100	240000	500	5519424	120017	120179	120042	89955	3	90008	240100	200	240119	200	480000	120042	120040	1	1	80201	100	99	0	100	100	80000	80000	100	240000	0	34	0	0	240000	0	0	2	240002	2	34	0	0	5110	1	16	1	1	120046	0	240000	100	120051	120043	120043	120043	120043
240204	120042	930	0	0	0	0	0	0	3	0	0	120584	16	16	0	25	240100	100	240060	100	240108	500	5543016	120137	120042	120042	89955	3	90000	240100	200	240000	200	480000	120049	120042	1	1	80201	100	99	0	100	100	80000	80000	100	240000	0	0	0	0	240002	0	0	2	240002	2	34	0	0	5110	1	16	1	1	120039	0	240000	100	120043	120041	120052	120043	120051
240204	120051	930	0	0	0	0	0	0	6	0	0	120036	16	16	0	25	240100	100	240000	100	240000	500	5519424	120017	120042	120042	89955	3	90000	240100	200	240000	200	480000	120042	120050	1	1	80201	100	99	0	100	100	80000	80000	100	240062	0	0	0	0	240002	5	0	2	240002	2	34	0	0	5110	1	16	1	1	120158	0	240000	100	120043	120043	120043	120043	120052
240204	120042	930	0	0	0	0	0	0	3	0	0	120027	16	16	0	25	240100	100	240000	100	240000	500	5519760	120017	120040	120042	89955	3	90007	240100	200	240000	200	480000	120042	120042	2	1	80201	100	99	0	100	100	80000	80000	100	240000	0	34	28	0	240002	0	0	5	240002	2	34	0	0	5110	1	16	1	1	120039	0	240000	100	120191	120043	120050	120043	120043
240204	120042	931	0	0	0	0	0	6	3	0	0	120027	16	16	0	25	240100	100	240000	100	240000	500	5519808	120015	120049	120042	89955	3	90055	240208	200	240000	200	480000	120050	120042	1	1	80201	100	99	0	100	100	80000	80000	100	240120	4	34	0	0	240062	0	0	1595	240002	2	34	0	2	5134	2	35	1	1	122735	24	240000	100	120331	120179	120567	120322	120459
240204	120322	934	0	1	0	3	1	264	179	0	0	120314	16	16	148	86	240176	124	240180	112	240108	590	5524164	120258	120326	120456	90142	41	90226	240332	200	240119	200	480238	120322	120321	4	1	80201	100	99	0	100	100	80000	80000	100	240000	0	34	0	0	240002	2	0	2	240002	2	34	0	0	5110	1	16	1	1	120039	0	240000	100	120043	120041	120043	120043	120043
240204	120042	931	0	0	0	0	0	18	3	0	0	120595	16	16	0	25	240100	100	240000	100	240000	565	5519424	120032	120042	120042	89955	3	90000	240100	200	240000	200	480000	120051	120042	1	1	80201	100	99	0	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	8	240002	2	40	0	0	5110	1	16	1	1	120047	0	240000	100	120052	120043	120043	120043	120043
240204	120042	930	0	0	0	0	0	12	9	0	0	120028	16	16	0	25	240100	100	240000	100	240000	500	5520192	120017	120042	120042	89953	3	90000	240100	200	240000	200	480000	120040	120051	1	1	80201	100	99	0	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	2	240002	2	0	0	0	5110	1	16	1	1	120039	0	240000	100	120043	120043	120041	120043	120043
240204	120049	931	0	0	0	0	0	0	9	0	0	120028	16	16	0	25	240100	100	240000	100	240000	500	5519424	120017	120042	120042	89955	3	90007	240100	200	240000	200	480000	120042	120049	1	1	80201	100	99	0	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	8	240002	2	34	0	0	5110	1	16	1	1	120039	0	240000	100	120043	120043	120043	120050	120041
240204	120042	931	0	0	0	0	0	12	3	0	0	120027	16	16	0	25	240100	100	240000	100	240000	500	5519352	120017	120042	120042	89955	3	90000	240100	200	240000	200	480000	120042	120042	1	1	80201	100	99	0	100	100	80000	80000	100	240000	0	0	0	0	240002	1	0	2	240002	2	34	0	0	5110	1	16	1	1	120048	0	240000	100	120041	120043	120051	120043	120043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9e	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b8	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	120052	930	1	1	0	0	1	0	0	0	14	0	1	120039	16	16	7	25	240010	10	240000	10	240000	50	5520028	0	120029	120054	120054	89998	3	90034	240010	20	240000	20	480000	120063	120042	1	1	80021	10	9	10	10	80000	80000	0	10	240015	0	44	0	0	240016	0	0	16	240002	0	16	44	0	0	5020	0	13	16	0	0	13	11	120051	0	0	240000	10	120053	120055	120055	120052	120048
240024	120052	930	1	1	0	0	1	0	0	0	17	0	1	120040	16	16	0	25	240010	10	240000	10	240000	50	5519448	0	120022	120054	120047	89987	3	90032	240010	20	240000	20	480000	120042	120054	1	1	80021	10	9	10	10	80000	80000	0	10	240014	15	42	0	0	240014	4	1	807	240002	0	2	44	14	0	5020	0	13	16	0	0	12	10	120050	0	0	240000	10	120055	120053	120055	120055	120055
240025	120054	930	0	1	0	0	0	0	0	12	14	0	1	120032	16	16	2	25	240010	10	240000	10	240000	50	5520076	0	120029	120042	120054	89998	3	90032	240010	20	240000	20	480000	120054	120042	1	1	80021	10	9	10	10	80000	80000	0	10	240014	14	44	1	0	240016	0	0	22	240002	0	16	0	14	0	5020	0	13	16	0	0	13	13	120061	0	13	240000	10	120055	120053	120055	120055	120183
240024	120047	930	1	0	0	0	1	0	0	0	21	0	1	120039	16	16	2	25	240010	10	240000	10	240000	50	5520028	0	120038	120063	120054	89989	16	90022	240010	20	240000	20	480000	120052	120054	1	1	80021	10	9	10	10	80000	80000	0	10	240014	14	50	0	0	240016	0	1	5	240002	0	2	44	14	0	5020	0	6	16	0	0	13	13	120050	0	10	240000	10	120055	120043	120053	120055	120055
240024	120054	930	0	0	0	0	1	0	0	12	91	0	1	120027	16	16	1	56	240010	10	240000	10	240000	50	5520028	0	120026	120052	120054	89989	3	90034	240010	20	240000	20	480000	120052	120054	2	1	80021	10	9	10	10	80000	80000	0	10	240015	14	44	0	0	240002	0	0	20	240002	0	16	48	14	0	5020	0	13	16	0	0	13	8	120044	0	0	240000	10	120044	120055	120053	120048	120044
240024	120047	930	1	0	0	0	1	0	0	0	17	0	1	120175	16	16	79	25	240010	10	240000	10	240000	50	5520004	0	120026	120052	120054	89996	3	90034	240010	20	240000	20	480000	120192	120054	1	1	80021	10	9	10	10	80000	80000	0	10	240000	14	44	31	0	240016	0	0	21	240002	0	16	42	14	0	5020	0	13	25	0	0	6	13	120040	0	0	240000	10	120055	120044	120204	120044	120055
240024	120054	931	1	0	0	0	0	0	1	0	3	0	1	120027	16	16	1	25	240010	10	240000	10	240000	50	5519908	0	120029	125897	126202	89988	3	90034	240010	20	240000	20	480240	120054	120051	1	1	80021	10	9	10	10	80000	80000	0	10	240015	0	44	0	0	240002	1	0	16	240002	0	16	44	0	1	5020	0	6	16	0	0	6	13	120051	0	0	240000	10	120056	120055	120043	120055	120055
240024	120042	931	1	0	0	0	0	0	0	12	17	0	1	120037	16	16	6	25	240010	10	240000	10	240000	50	5524308	0	120029	120054	120051	89989	3	90034	240010	20	240000	20	480000	120043	120052	1	1	80021	10	9	10	10	80000	80000	0	10	240000	14	42	0	1	240016	0	1	19	240002	0	16	42	14	0	5020	0	6	16	0	0	13	6	120039	0	20	240000	10	120055	120056	120053	120044	120055
240024	120063	930	1	0	0	0	0	0	0	0	19	0	1	120039	16	16	2	25	240010	10	240000	10	240000	50	5520439	0	120017	120054	120054	89986	16	90032	240010	20	240000	20	480000	120054	120042	1	1	80021	10	9	10	10	80000	80000	0	10	240015	0	44	0	0	240074	0	0	16	240002	0	14	48	0	1	5020	0	13	16	0	0	13	13	120051	0	0	240000	10	120054	120048	120055	120054	120053
240024	120043	931	1	0	0	0	0	0	0	0	17	0	0	120039	15	16	1	25	240010	10	240000	10	240000	50	5519908	0	120029	120054	120191	89988	3	90034	240010	20	240000	20	480000	120043	120052	1	1	80021	10	9	10	10	80000	80000	0	10	240014	14	44	0	1	240016	0	0	2	240062	0	2	44	14	0	5020	0	12	16	0	0	13	8	120049	0	0	240000	10	120055	120053	120064	120055	120055

ST1 (multiple, 3 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations