Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st1 { v0.8b, v1.8b, v2.8b }, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 60 nops): 3.000
Issues: 3.000
Integer unit issues: 0.000
Load/store unit issues: 2.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | l1d cache miss st nonspec (c0) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
63006 | 28873 | 224 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4849 | 28606 | 0 | 0 | 17918 | 3000 | 1000 | 2000 | 1000 | 2000 | 15905 | 8000 | 7 | 21715 | 28425 | 28637 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 28888 | 28798 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 6 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 13152 | 9546 | 6925 | 3154 | 0 | 44 | 20329 | 3148 | 3818 | 43 | 30 | 36 | 28473 | 15827 | 12922 | 14625 | 2000 | 1000 | 29042 | 28910 | 28994 | 28957 | 28979 |
63004 | 28974 | 225 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4662 | 28723 | 3 | 0 | 18000 | 3000 | 1000 | 2000 | 1000 | 2000 | 15903 | 8000 | 9 | 21695 | 28667 | 28955 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 28796 | 29069 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 6 | 0 | 2000 | 0 | 0 | 0 | 2000 | 6 | 0 | 0 | 13246 | 9657 | 6940 | 3208 | 1 | 42 | 20308 | 3241 | 3816 | 44 | 39 | 44 | 28428 | 15860 | 12929 | 14336 | 2000 | 1000 | 28947 | 29102 | 29044 | 29015 | 29098 |
63004 | 28896 | 224 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 4689 | 28733 | 3 | 0 | 17894 | 3000 | 1000 | 2000 | 1000 | 2000 | 15902 | 8000 | 6 | 21692 | 28737 | 29067 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 28940 | 28962 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13210 | 9497 | 6979 | 3155 | 0 | 38 | 20292 | 3193 | 3813 | 48 | 35 | 40 | 28478 | 15787 | 12889 | 14428 | 2000 | 1000 | 29077 | 29137 | 29248 | 29084 | 29038 |
63004 | 29224 | 227 | 0 | 2 | 0 | 1 | 1 | 1 | 2 | 132 | 88 | 0 | 0 | 4622 | 28726 | 2 | 0 | 18062 | 3006 | 1001 | 2002 | 1002 | 2002 | 15991 | 8008 | 6 | 21718 | 28700 | 29058 | 8 | 29 | 3000 | 2002 | 1000 | 4004 | 2002 | 28935 | 29351 | 8 | 1 | 61001 | 1000 | 1000 | 2000 | 4 | 0 | 2000 | 0 | 4 | 786 | 2002 | 0 | 4 | 0 | 13159 | 9426 | 6929 | 3092 | 0 | 43 | 20482 | 3215 | 3814 | 46 | 41 | 37 | 28545 | 15732 | 13225 | 14753 | 2000 | 1000 | 29163 | 29087 | 29104 | 29168 | 29204 |
63004 | 29138 | 226 | 0 | 1 | 1 | 1 | 1 | 3 | 2 | 537 | 352 | 0 | 0 | 4614 | 28964 | 0 | 0 | 18194 | 3003 | 1000 | 2000 | 1000 | 2000 | 15905 | 8000 | 6 | 21688 | 28776 | 29179 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 28939 | 29047 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 3 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 567 | 13043 | 9654 | 6877 | 3184 | 0 | 35 | 20505 | 3254 | 3819 | 40 | 38 | 43 | 28742 | 15682 | 12915 | 14716 | 2000 | 1000 | 29732 | 29627 | 29466 | 29698 | 29626 |
63004 | 29531 | 230 | 0 | 2 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4433 | 29207 | 0 | 0 | 18559 | 3000 | 1000 | 2000 | 1000 | 2000 | 15904 | 8000 | 3 | 21721 | 29104 | 29571 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29440 | 29508 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 4 | 0 | 2000 | 1 | 0 | 0 | 2000 | 4 | 0 | 0 | 12790 | 9019 | 6864 | 2994 | 1 | 33 | 20919 | 3109 | 3818 | 37 | 42 | 40 | 28607 | 16830 | 13888 | 15401 | 2000 | 1000 | 29493 | 29532 | 29581 | 29499 | 29543 |
63004 | 29585 | 230 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4630 | 29244 | 0 | 0 | 18583 | 3000 | 1000 | 2000 | 1000 | 2000 | 15908 | 8000 | 3 | 21754 | 29183 | 29649 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29499 | 29485 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 2180 | 12758 | 9210 | 6820 | 3043 | 0 | 34 | 20868 | 3291 | 3817 | 35 | 38 | 43 | 28671 | 16563 | 13660 | 15522 | 2000 | 1000 | 29632 | 29661 | 29668 | 29526 | 29483 |
63004 | 29592 | 221 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4549 | 29213 | 2 | 0 | 18549 | 3000 | 1000 | 2000 | 1000 | 2000 | 15902 | 8000 | 3 | 21724 | 29041 | 29560 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29454 | 29485 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 6 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 12881 | 8884 | 6810 | 3038 | 0 | 32 | 20853 | 3132 | 3815 | 39 | 40 | 37 | 28666 | 16761 | 13857 | 15413 | 2000 | 1000 | 29597 | 29664 | 29567 | 29576 | 29577 |
63004 | 29550 | 221 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4561 | 29162 | 0 | 0 | 18521 | 3000 | 1000 | 2000 | 1000 | 2000 | 15906 | 8000 | 4 | 21726 | 29147 | 29588 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29483 | 29445 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 12975 | 9181 | 6812 | 3073 | 1 | 34 | 20897 | 3097 | 3815 | 39 | 35 | 34 | 28663 | 16778 | 13718 | 15448 | 2000 | 1000 | 29549 | 29510 | 29486 | 29524 | 29549 |
63004 | 29551 | 221 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4530 | 29222 | 0 | 0 | 18587 | 3000 | 1000 | 2000 | 1000 | 2000 | 15906 | 8000 | 7 | 21683 | 29135 | 29509 | 3 | 10 | 3000 | 2000 | 1000 | 4000 | 2000 | 29419 | 29416 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 2000 | 2 | 0 | 0 | 2000 | 0 | 0 | 0 | 12827 | 9109 | 6843 | 3014 | 1 | 29 | 20824 | 3103 | 3817 | 44 | 34 | 38 | 28614 | 16715 | 13786 | 15491 | 2000 | 1000 | 29524 | 29488 | 29549 | 29594 | 29496 |
Count: 8
Code:
st1 { v0.8b, v1.8b, v2.8b }, [x6] st1 { v0.8b, v1.8b, v2.8b }, [x6] st1 { v0.8b, v1.8b, v2.8b }, [x6] st1 { v0.8b, v1.8b, v2.8b }, [x6] st1 { v0.8b, v1.8b, v2.8b }, [x6] st1 { v0.8b, v1.8b, v2.8b }, [x6] st1 { v0.8b, v1.8b, v2.8b }, [x6] st1 { v0.8b, v1.8b, v2.8b }, [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0007
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 23 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | da | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
240206 | 80064 | 621 | 1 | 1 | 0 | 4 | 3 | 594 | 403 | 0 | 328 | 1 | 80557 | 16 | 0 | 5 | 25 | 240241 | 100 | 80047 | 160000 | 100 | 80000 | 160000 | 500 | 3679967 | 642082 | 80030 | 80054 | 80053 | 49960 | 3 | 50012 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80063 | 80064 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 44 | 0 | 1 | 160016 | 0 | 1 | 18 | 160002 | 16 | 44 | 14 | 2 | 5110 | 2 | 16 | 2 | 2 | 2 | 80049 | 0 | 0 | 160000 | 80000 | 100 | 80055 | 80064 | 80054 | 80055 | 80053 |
240204 | 80064 | 621 | 1 | 0 | 1 | 0 | 0 | 0 | 17 | 0 | 42 | 1 | 80040 | 16 | 16 | 1 | 25 | 240137 | 100 | 80006 | 160000 | 100 | 80000 | 160000 | 500 | 3680039 | 640099 | 80027 | 80054 | 80054 | 49960 | 3 | 50012 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80052 | 80052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 14 | 0 | 0 | 0 | 160016 | 0 | 0 | 16 | 160002 | 16 | 44 | 14 | 0 | 5110 | 2 | 16 | 2 | 2 | 3 | 80051 | 0 | 0 | 160000 | 80000 | 100 | 80053 | 80055 | 80055 | 80052 | 80055 |
240204 | 80054 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 20 | 0 | 1030 | 1 | 80039 | 16 | 0 | 1 | 25 | 240111 | 100 | 80556 | 160000 | 100 | 80000 | 160000 | 500 | 3680039 | 640183 | 80030 | 80053 | 80052 | 49967 | 3 | 50010 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80054 | 80054 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 15 | 44 | 0 | 0 | 160016 | 0 | 0 | 16 | 160002 | 16 | 44 | 14 | 1 | 5110 | 2 | 16 | 0 | 3 | 2 | 80051 | 0 | 0 | 160000 | 80000 | 100 | 80064 | 80053 | 80055 | 80065 | 80055 |
240204 | 80052 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 55 | 1 | 80039 | 16 | 16 | 5 | 25 | 240142 | 100 | 80042 | 160000 | 100 | 80000 | 160000 | 500 | 3680063 | 640082 | 80039 | 80055 | 80055 | 49960 | 3 | 50012 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80047 | 80063 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 44 | 0 | 1 | 160016 | 1 | 1 | 14 | 160002 | 16 | 44 | 14 | 0 | 5110 | 2 | 16 | 0 | 2 | 1 | 80051 | 0 | 0 | 160000 | 80000 | 100 | 80048 | 80055 | 80055 | 80053 | 80055 |
240204 | 80054 | 620 | 1 | 0 | 1 | 0 | 0 | 0 | 18 | 1 | 1037 | 1 | 80040 | 15 | 16 | 6 | 25 | 240760 | 100 | 80815 | 160000 | 100 | 80000 | 160000 | 565 | 3695277 | 640776 | 80031 | 80054 | 80054 | 49965 | 3 | 50005 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80047 | 80054 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 14 | 44 | 0 | 1 | 160016 | 1 | 1 | 14 | 160002 | 16 | 44 | 14 | 0 | 5110 | 3 | 16 | 0 | 2 | 1 | 80060 | 0 | 0 | 160000 | 80000 | 100 | 80055 | 80048 | 80054 | 80055 | 80064 |
240204 | 80054 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 18 | 0 | 36 | 1 | 80038 | 16 | 16 | 3 | 25 | 241187 | 100 | 80040 | 160000 | 100 | 80000 | 160000 | 500 | 3679966 | 640169 | 80027 | 80063 | 80052 | 49967 | 3 | 50012 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80051 | 80052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 14 | 44 | 0 | 1 | 160016 | 0 | 0 | 17 | 160002 | 16 | 44 | 14 | 0 | 5110 | 3 | 16 | 0 | 2 | 2 | 80049 | 0 | 0 | 160000 | 80000 | 100 | 80055 | 80053 | 80055 | 80055 | 80048 |
240204 | 80063 | 621 | 1 | 0 | 0 | 0 | 0 | 12 | 17 | 0 | 36 | 1 | 80048 | 16 | 16 | 6 | 25 | 240919 | 100 | 80679 | 160000 | 100 | 80000 | 160000 | 500 | 3680472 | 642622 | 80028 | 80063 | 80064 | 49967 | 3 | 50013 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80052 | 80052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 15 | 44 | 0 | 1 | 160016 | 0 | 0 | 16 | 160002 | 16 | 46 | 14 | 0 | 5110 | 3 | 16 | 0 | 2 | 1 | 80048 | 0 | 0 | 160000 | 80000 | 100 | 80055 | 80053 | 80055 | 80055 | 80048 |
240204 | 80052 | 621 | 1 | 1 | 0 | 0 | 0 | 0 | 20 | 1 | 905 | 1 | 80040 | 16 | 16 | 2 | 25 | 241109 | 100 | 80029 | 160000 | 100 | 80000 | 160000 | 500 | 3680037 | 641029 | 80029 | 80043 | 80043 | 49953 | 3 | 50001 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80043 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 42 | 0 | 0 | 160000 | 0 | 0 | 5 | 160002 | 2 | 42 | 0 | 0 | 5110 | 3 | 16 | 0 | 2 | 2 | 80040 | 0 | 0 | 160000 | 80000 | 100 | 80041 | 80041 | 80044 | 80044 | 80044 |
240204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 37 | 0 | 80025 | 16 | 16 | 1 | 25 | 240113 | 100 | 80028 | 160000 | 100 | 80000 | 160000 | 500 | 3679508 | 640139 | 80018 | 80040 | 80040 | 49956 | 3 | 50001 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80043 | 80043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 0 | 0 | 0 | 160002 | 0 | 0 | 6 | 160000 | 2 | 0 | 0 | 0 | 5110 | 2 | 16 | 0 | 2 | 1 | 80040 | 0 | 0 | 160000 | 80000 | 100 | 80044 | 80041 | 80041 | 80041 | 80044 |
240204 | 80047 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 26 | 0 | 80028 | 16 | 16 | 1 | 25 | 240128 | 100 | 80037 | 160000 | 100 | 80059 | 160000 | 500 | 3679388 | 640147 | 80018 | 80043 | 80043 | 49953 | 3 | 50001 | 240100 | 200 | 160000 | 80000 | 200 | 320000 | 160000 | 80043 | 80043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 42 | 0 | 0 | 160000 | 0 | 0 | 3 | 160002 | 2 | 42 | 0 | 0 | 5110 | 3 | 16 | 0 | 1 | 1 | 80040 | 0 | 0 | 160000 | 80000 | 100 | 80044 | 80044 | 80044 | 80041 | 80044 |
Result (median cycles for code divided by count): 1.0007
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
240026 | 80053 | 621 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 1204 | 2 | 80048 | 0 | 0 | 0 | 25 | 240011 | 10 | 80513 | 160000 | 10 | 80000 | 160000 | 50 | 3680472 | 642118 | 0 | 80029 | 0 | 80054 | 80053 | 49999 | 3 | 50044 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80054 | 80054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160014 | 15 | 44 | 0 | 1 | 160016 | 0 | 1 | 17 | 160002 | 16 | 44 | 14 | 0 | 0 | 0 | 5020 | 1 | 16 | 1 | 1 | 80051 | 0 | 160000 | 80000 | 10 | 85124 | 84964 | 82403 | 81398 | 80053 |
240024 | 80052 | 621 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 12 | 20 | 0 | 0 | 660 | 2 | 80037 | 16 | 16 | 2 | 25 | 240879 | 10 | 81023 | 160000 | 10 | 80000 | 160000 | 60 | 3680541 | 644771 | 0 | 80027 | 0 | 80055 | 80054 | 49989 | 3 | 50044 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80054 | 80054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160014 | 14 | 44 | 0 | 2 | 160016 | 0 | 0 | 19 | 160002 | 16 | 44 | 14 | 0 | 0 | 0 | 5022 | 1 | 16 | 2 | 1 | 80051 | 2 | 160000 | 80000 | 10 | 80054 | 80055 | 80064 | 80055 | 80064 |
240024 | 80052 | 621 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 2 | 1 | 80039 | 16 | 16 | 2 | 25 | 241047 | 10 | 81073 | 160000 | 10 | 80000 | 160000 | 50 | 3680109 | 640018 | 0 | 80027 | 0 | 80052 | 80052 | 49989 | 3 | 50032 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80063 | 80064 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160014 | 14 | 44 | 0 | 1 | 160016 | 1 | 1 | 18 | 160002 | 16 | 44 | 14 | 1 | 0 | 0 | 5020 | 2 | 16 | 1 | 2 | 80051 | 0 | 160000 | 80000 | 10 | 80055 | 80053 | 80055 | 80055 | 80055 |
240024 | 80053 | 621 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 132 | 14 | 0 | 0 | 1346 | 2 | 80040 | 15 | 16 | 108 | 25 | 240735 | 10 | 80872 | 160000 | 10 | 80000 | 160000 | 50 | 3680039 | 641187 | 0 | 80039 | 0 | 80056 | 80054 | 49989 | 3 | 50034 | 240010 | 20 | 160122 | 80000 | 20 | 320000 | 160000 | 80054 | 80054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160015 | 14 | 43 | 0 | 0 | 160016 | 0 | 1 | 16 | 160002 | 16 | 44 | 14 | 0 | 0 | 0 | 5022 | 2 | 16 | 1 | 1 | 80052 | 0 | 160000 | 80000 | 10 | 80064 | 80055 | 80055 | 80053 | 80055 |
240024 | 80054 | 621 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 19 | 0 | 0 | 6 | 2 | 80039 | 16 | 16 | 2 | 25 | 240438 | 10 | 80837 | 160000 | 10 | 80000 | 160000 | 50 | 3680061 | 640012 | 0 | 80180 | 0 | 80052 | 80052 | 49989 | 3 | 50032 | 240010 | 20 | 160000 | 80000 | 20 | 320246 | 160000 | 80063 | 80052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160014 | 14 | 44 | 0 | 0 | 160016 | 2 | 1 | 16 | 160002 | 16 | 48 | 14 | 0 | 0 | 0 | 5020 | 1 | 16 | 1 | 1 | 80051 | 0 | 160000 | 80000 | 10 | 80055 | 80053 | 80222 | 80053 | 80055 |
240024 | 80054 | 620 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 12 | 17 | 0 | 0 | 1421 | 1 | 80037 | 16 | 16 | 0 | 25 | 240011 | 10 | 80908 | 160000 | 10 | 80059 | 160000 | 50 | 3680157 | 640945 | 0 | 80026 | 0 | 80064 | 80229 | 49982 | 3 | 50032 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80054 | 80054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160015 | 15 | 44 | 0 | 0 | 160016 | 1 | 1 | 16 | 160002 | 16 | 44 | 14 | 0 | 0 | 0 | 5020 | 1 | 16 | 2 | 1 | 80051 | 0 | 160000 | 80000 | 10 | 80055 | 80054 | 80055 | 80055 | 80055 |
240024 | 80053 | 620 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 22 | 1 | 0 | 5 | 2 | 80039 | 16 | 16 | 1 | 25 | 240014 | 10 | 80404 | 160000 | 10 | 80000 | 160000 | 50 | 3680063 | 640018 | 0 | 80029 | 0 | 80054 | 80054 | 49986 | 3 | 50034 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80054 | 80054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160015 | 14 | 44 | 63 | 0 | 160016 | 0 | 2 | 16 | 160002 | 16 | 44 | 14 | 0 | 0 | 0 | 5037 | 2 | 16 | 3 | 1 | 80206 | 0 | 160000 | 80000 | 10 | 80223 | 80048 | 80055 | 80053 | 80224 |
240024 | 80398 | 621 | 1 | 0 | 0 | 1 | 2 | 2 | 0 | 396 | 107 | 0 | 0 | 12 | 2 | 80207 | 16 | 16 | 111 | 46 | 240542 | 10 | 80418 | 160120 | 10 | 80118 | 160108 | 55 | 3699669 | 641366 | 0 | 80338 | 0 | 80381 | 80397 | 50229 | 8 | 50303 | 240177 | 20 | 160122 | 80124 | 20 | 320768 | 160122 | 80223 | 80405 | 2 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 161097 | 14 | 44 | 969 | 0 | 160076 | 0 | 0 | 2842 | 160122 | 16 | 44 | 14 | 0 | 0 | 0 | 5037 | 2 | 34 | 2 | 1 | 80357 | 1 | 160000 | 80000 | 10 | 80223 | 80221 | 80391 | 80228 | 80226 |
240024 | 80384 | 622 | 1 | 1 | 2 | 0 | 2 | 2 | 0 | 12 | 17 | 0 | 0 | 8 | 1 | 80037 | 16 | 0 | 1 | 25 | 240692 | 10 | 80003 | 160000 | 10 | 80000 | 160000 | 50 | 3679941 | 640023 | 0 | 80029 | 0 | 80054 | 80054 | 49989 | 3 | 50027 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80054 | 80054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160015 | 14 | 42 | 0 | 1 | 160016 | 0 | 0 | 23 | 160002 | 16 | 0 | 14 | 0 | 0 | 0 | 5020 | 1 | 16 | 1 | 1 | 80049 | 0 | 160000 | 80000 | 10 | 80048 | 80055 | 80055 | 80053 | 80055 |
240024 | 80054 | 620 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 685 | 1 | 80039 | 16 | 15 | 0 | 25 | 240012 | 10 | 80728 | 160000 | 10 | 80000 | 160000 | 50 | 3679966 | 640010 | 0 | 80027 | 0 | 80054 | 80054 | 49982 | 3 | 50034 | 240010 | 20 | 160000 | 80000 | 20 | 320000 | 160000 | 80052 | 80064 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160015 | 14 | 44 | 0 | 2 | 160016 | 1 | 0 | 18 | 160002 | 16 | 44 | 14 | 0 | 0 | 0 | 5022 | 2 | 16 | 2 | 2 | 80051 | 0 | 160000 | 80000 | 10 | 80064 | 80054 | 80055 | 80053 | 80048 |