Firestorm: ST1 (multiple, 3 regs, 8H) measurements

Code:

  st1 { v0.8h, v1.8h, v2.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
63005	28765	222	0	2	0	0	3	0	0	0	0	1	0	0	4763	28548	0	0	22595	3000	3000	3000	15899	0	17056	28191	28647	3	10	3000	3000	6000	28533	28625	1	1	61001	1000	1000	3000	0	6	3000	0	0	3003	0	6	0	0	13206	9428	7055	3068	1	35	20101	3294	3819	14	37	34	28224	15487	12119	14337	3000	28719	28663	28650	28733	28688
63004	28735	222	0	2	0	0	2	0	0	0	0	1	0	0	4702	28534	0	0	22662	3000	3000	3000	15906	3	17050	28241	28719	3	10	3000	3000	6000	28552	28651	1	1	61001	1000	1000	3000	0	0	3000	0	465	3000	0	6	0	0	13461	9487	7038	3126	0	39	19969	3262	3818	16	36	41	28185	15242	12429	14097	3000	28692	28598	28774	28645	28649
63004	28654	223	0	1	0	0	3	0	0	0	0	1	0	0	4677	28545	0	0	22670	3000	3000	3000	15906	2	17049	28081	28686	3	10	3000	3000	6000	28696	28620	1	1	61001	1000	1000	3000	0	6	3000	0	0	3003	0	6	0	0	13083	9528	7025	3156	0	41	19961	3193	3815	16	39	38	28166	15302	12501	14000	3000	28680	28748	28676	28744	28769
63004	28779	222	0	2	0	0	2	0	0	0	0	1	0	0	4724	28637	0	0	22662	3000	3000	3000	15900	3	17033	28087	28696	3	10	3003	3000	6000	28654	28592	1	1	61001	1000	1000	3000	2	6	3000	0	0	3000	0	6	0	256	13223	9582	6966	3224	0	37	20038	3220	3819	19	35	32	28169	15262	12550	13948	3000	28695	28661	28806	28872	28682
63004	28607	223	0	0	0	0	2	0	0	0	162	1	0	0	4719	28620	0	0	22629	3000	3000	3000	15902	4	17041	28131	28765	3	10	3000	3000	6000	28591	28713	1	1	61001	1000	1000	3000	0	0	3000	0	0	3000	0	6	0	0	13352	9583	6931	3194	1	42	20081	3221	3818	15	40	38	28205	15481	12311	14085	3000	28699	28733	28572	28669	28752
63004	28784	223	0	3	0	1	2	0	0	1	0	0	1	0	4829	28572	1	0	22592	3000	3000	3000	15904	3	17058	28121	28753	3	10	3000	3000	6000	28669	28615	1	1	61001	1000	1000	3000	2	0	3000	0	0	3000	0	6	0	0	13269	9352	7042	3207	1	40	20185	3207	3817	16	39	42	28226	15568	12583	14161	3000	28804	28628	28746	28871	28814
63004	28701	223	0	2	1	0	1	0	0	1	0	0	1	0	4723	28634	0	0	22689	3000	3000	3000	15901	2	17019	28219	28698	3	10	3000	3000	6000	28682	28675	1	1	61001	1000	1000	3000	2	0	3000	0	0	3000	0	6	2	0	13483	9492	7039	3164	0	42	20002	3220	3818	18	38	41	28135	15601	12628	13958	3000	28695	28686	28725	28691	28628
63004	28684	223	0	1	0	0	3	0	1	0	0	1	1	0	4785	28482	0	0	22621	3000	3000	3000	15912	7	17047	28117	28800	3	10	3000	3000	6006	28583	28645	1	1	61001	1000	1000	3000	0	6	3000	0	0	3000	0	6	0	0	13447	9393	6973	3153	1	45	20009	3290	3812	14	36	34	28177	15709	12614	13964	3000	28696	28629	28716	28688	28712
63004	28724	222	0	1	0	0	0	0	0	0	0	1	0	0	4720	28535	0	0	22678	3000	3000	3000	15904	2	17036	28096	28697	3	10	3000	3000	6000	28536	28668	1	1	61001	1000	1000	3000	0	0	3000	0	0	3000	0	6	0	0	13244	9503	7041	3135	1	35	20040	3349	3820	20	35	35	28146	15623	12404	13869	3000	28762	28800	28742	28656	28652
63004	28798	222	0	1	0	0	1	0	0	0	9	1	0	0	4698	28617	0	0	22607	3000	3000	3000	15908	4	17069	28171	28763	3	10	3000	3000	6000	28598	28630	1	1	61001	1000	1000	3000	0	6	3000	0	478	3000	0	6	0	0	13290	9621	6959	3183	1	38	20094	3309	3820	9	35	33	28160	15389	12624	14201	3000	28722	28726	28664	28652	28761

Count: 8

Code:

  st1 { v0.8h, v1.8h, v2.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	23	3f	46	49	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	120063	930	1	0	1	0	0	48	3	0	120027	16	16	2	2	25	240100	100	240000	105	240000	500	5519448	0	120137	0	120043	120048	89959	3	90011	240100	200	240000	200	480000	120042	120042	3	1	80201	100	99	100	100	80000	80000	100	240000	0	42	126	0	240002	2	0	5	240002	0	42	0	0	0	5110	0	0	1	16	2	1	120039	0	240000	100	120043	120043	120044	120045	120043
240204	120042	930	0	0	0	0	0	12	3	0	120122	0	16	73	0	25	240100	100	240000	100	240000	500	5519448	0	120017	0	120042	120042	89955	3	90012	240100	200	240000	200	480240	120042	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	2	42	0	0	240000	1	0	5	240002	2	0	0	0	0	5110	0	0	1	16	1	1	120039	0	240000	100	120043	120043	120041	120047	120043
240204	120184	930	0	0	0	0	0	0	3	0	120025	16	16	0	0	25	240100	100	240000	100	240000	500	5519448	0	120017	0	120042	120040	89956	3	90000	240100	200	240000	200	480000	120042	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240002	0	0	0	240002	2	42	0	0	0	5110	0	0	1	16	1	1	120039	0	240000	100	120043	120043	120052	120045	120044
240204	120042	930	0	0	0	0	0	24	3	0	120027	16	16	0	0	25	240100	100	240000	100	240000	500	5524332	0	120018	0	120042	120043	89957	3	90003	240100	200	240000	200	480000	120042	120207	2	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240002	0	0	2	240002	2	42	0	0	0	5110	0	0	1	16	1	1	120039	0	240000	100	120043	120047	120053	120043	120044
240204	120042	930	0	0	0	0	0	12	3	0	120028	16	16	1	0	25	240100	120	240000	100	240000	500	5519472	0	120017	0	120040	120042	89955	3	89998	240100	200	240000	200	480000	120042	120042	3	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240002	1	0	2	240002	2	42	0	0	0	5110	0	0	1	25	1	1	120039	0	240000	100	120043	120183	120054	120041	120043
240204	120042	931	0	0	0	0	0	0	3	0	120028	0	16	1	0	25	240100	100	240000	100	240108	500	5519352	0	120017	0	120042	120042	89955	3	90001	240208	200	240000	200	480000	120042	120040	1	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240002	0	0	0	240000	2	0	0	0	0	5110	0	0	1	16	1	1	120039	0	240000	100	120043	120047	120046	120043	120041
240204	120040	931	0	0	0	0	0	0	0	0	120027	16	16	1	0	25	240185	100	240000	100	240000	500	5519472	0	120017	3	120040	120042	89953	3	90001	240100	200	240000	200	480000	120042	120184	1	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240002	0	0	0	240002	0	42	0	0	0	5110	0	0	1	16	1	1	120039	0	240000	100	120185	120043	120047	120043	120043
240204	120042	931	0	0	0	0	0	12	3	0	120027	16	16	1	0	25	240100	100	240000	100	240000	500	5519448	0	120017	0	120040	120042	89955	3	90000	240100	200	240000	200	480000	120042	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240062	0	0	2	240002	2	42	0	0	0	5110	0	0	1	16	1	1	120039	5	240000	100	120043	120050	120047	120184	120044
240204	120042	930	0	0	0	0	0	0	3	0	120028	16	16	77	0	25	240180	100	240000	100	240000	500	5519448	0	120017	0	120042	120042	90304	3	90000	240317	200	240000	200	480000	120042	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240002	1	0	2	240002	2	42	0	0	0	5110	0	0	1	16	2	1	120039	0	240000	100	120043	120043	120041	120051	120043
240204	120054	931	0	0	0	0	0	0	3	0	120028	16	0	0	0	25	240100	100	240000	100	240000	500	5519472	0	120018	0	120042	120043	90046	3	90000	240100	200	240000	200	480240	120042	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	2	42	0	0	240002	0	0	6	240000	2	42	0	0	0	5110	0	0	2	16	1	1	120037	23	240000	100	120182	120326	120185	120470	120182

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	120042	931	0	0	0	0	0	0	0	3	0	0	0	120027	16	16	1	25	240010	10	240000	10	240000	50	5519448	0	120017	120042	120042	89977	3	90023	240010	20	240000	20	480000	120042	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	0	0	2	240002	2	42	0	0	5020	0	4	16	3	8	120039	0	240000	10	120043	120043	120043	120043	120043
240024	120040	930	0	0	0	0	0	0	9	3	0	0	0	120039	16	16	1	25	240010	10	240000	10	240000	50	5519448	0	120018	120042	120042	89989	3	90022	240010	20	240000	20	480000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	0	0	2	240002	2	42	0	0	5020	0	5	16	6	5	120039	0	240000	10	120043	120043	120043	120043	120043
240024	120042	931	0	0	0	0	0	0	0	3	0	0	0	120027	16	16	1	25	240010	10	240000	10	240000	50	5519448	0	120017	120042	120042	89977	3	90022	240010	20	240000	20	480000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	44	0	0	240002	0	0	2	240002	0	42	0	0	5020	0	5	16	5	4	120039	0	240000	10	120043	120044	120041	120043	120044
240024	120042	930	0	0	0	0	0	0	0	0	1	0	0	120028	16	16	0	25	240010	10	240000	10	240000	50	5519448	0	120021	120042	120043	89977	3	90022	240010	20	240000	20	480000	120043	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	0	0	2	240002	2	42	0	0	5020	0	4	16	5	5	120039	0	240000	10	120044	120043	120043	120044	120043
240024	120043	930	0	0	0	0	0	0	0	3	0	0	0	120027	16	16	0	25	240010	10	240000	10	240000	50	5519472	0	120017	120042	120042	89977	3	90022	240010	20	240000	20	480000	120044	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	2	0	2	240002	2	42	0	0	5020	0	4	16	3	3	120040	0	240000	10	120041	120041	120041	120043	120043
240024	120043	931	0	0	0	0	0	0	0	3	0	0	0	120027	16	16	1	25	240010	10	240000	10	240000	50	5519472	0	120021	120043	120042	89978	3	90023	240010	20	240000	20	480000	120043	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	0	0	2	240002	2	42	0	0	5020	0	5	16	4	4	120040	0	240000	10	120044	120044	120043	120043	120044
240024	120043	930	0	0	0	0	0	0	0	3	1	0	0	120027	16	16	1	25	240010	10	240000	10	240000	50	5519448	0	120017	120042	120042	89977	3	90022	240010	20	240000	20	480000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	0	0	2	240002	2	42	0	0	5020	0	3	16	3	4	120040	0	240000	10	120044	120043	120043	120044	120043
240024	120043	931	0	0	0	0	0	0	0	3	0	0	0	120027	16	16	1	25	240010	10	240000	10	240000	50	5520000	0	120017	120042	120042	89978	3	90022	240010	20	240000	20	480000	120043	120042	2	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	0	0	2	240002	2	42	0	0	5020	0	2	16	3	4	120039	0	240000	10	120043	120043	120045	120043	120600
240024	120043	964	0	0	1	0	0	0	0	3	0	0	0	120423	0	16	1	84	240010	10	240000	10	240000	50	5520000	0	120018	120042	120042	89977	28	90182	240010	20	240000	20	480000	120043	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	0	0	2	240002	0	42	0	0	5020	0	4	16	4	4	120051	0	240000	10	120043	120043	120043	120055	120043
240024	120042	930	0	0	0	0	0	0	30	3	1	0	0	120027	16	16	1	25	240010	10	240000	10	240000	50	5519448	0	121673	120483	120044	89979	3	90022	240010	20	240000	20	480000	120042	120043	1	1	80021	10	9	10	10	80000	80000	10	240060	0	42	0	0	240062	1	0	2	240722	2	42	0	0	5020	0	3	16	4	3	120039	0	240000	10	120043	120043	120044	120122	120043

ST1 (multiple, 3 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations