Firestorm: ST1 (multiple, 4 regs, 16B) measurements

Code:

  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
64005	28655	222	1	29	1	1	21	1	0	0	0	9	0	0	4846	28489	4	4	22536	4000	4000	4000	21639	13	17028	0	28055	28687	3	10	4000	4000	8000	28690	28571	1	1	61001	1000	1000	4005	4	0	0	4006	0	1	9	4002	4	14	4	0	0	13309	9522	6861	3178	15	70	19771	3157	3810	19	62	62	2	28110	15610	12681	14048	4000	28741	28662	28671	28622	28827
64004	28604	222	1	23	0	0	27	0	0	0	0	9	0	0	4851	28628	4	4	22541	4000	4000	4000	21621	14	17033	0	28110	28739	3	10	4000	4000	8000	28476	28685	1	1	61001	1000	1000	4004	5	0	1	4004	0	2	8	4002	6	14	4	2	0	13083	9321	6880	3115	14	65	19675	3126	3819	31	65	65	2	28154	15366	12568	13875	4000	28740	28692	28794	28555	28692
64004	28678	224	1	27	0	1	22	1	0	0	12	8	0	0	4776	28638	4	4	22570	4000	4000	4000	21606	9	17033	3	28103	28847	3	10	4000	4000	8000	28609	28683	1	1	61001	1000	1000	4005	5	0	2	4004	0	2	7	4002	4	8	4	1	0	13336	9613	6924	3164	16	66	19654	3094	3821	38	60	58	2	28206	15307	12548	14193	4000	28598	28798	28888	28840	28744
64004	28655	223	1	25	0	0	20	0	0	0	0	5	0	0	4641	28566	0	0	22638	4000	4000	4000	21629	5	17043	0	28133	28777	3	10	4000	4000	8000	28747	28636	1	1	61001	1000	1000	4004	5	8	1	4004	0	1	4	4000	4	0	4	1	0	13276	9397	7016	3175	14	64	19741	3138	3821	30	64	65	2	28146	15241	12657	14262	4000	28803	28598	28735	28647	28799
64004	28643	223	1	26	1	0	25	0	1	0	0	4	0	0	4895	28632	0	0	22703	4000	4000	4000	21632	9	17040	0	28119	28746	3	10	4000	4000	8000	28596	28575	1	1	61001	1000	1000	4004	5	8	2	4004	0	1	4	4000	4	8	4	0	0	13283	9470	6964	3280	14	69	19745	3192	3820	34	66	62	2	28096	15556	12746	14165	4000	28784	28748	28774	28655	28776
64004	28749	222	1	24	1	1	23	1	0	0	0	5	0	0	4698	28567	0	0	22720	4000	4000	4000	21635	9	17021	0	28183	28875	3	10	4000	4000	8000	28778	28574	1	1	61001	1000	1000	4005	5	8	1	4004	0	2	4	4000	4	0	4	1	0	13247	9528	6928	3184	14	61	19810	3167	3826	32	60	59	2	28152	15684	12493	13998	4000	28691	28808	28733	28579	28819
64004	28777	223	1	24	0	1	23	1	0	0	0	93	0	0	4787	28485	0	0	22589	4000	4000	4004	21639	9	17019	0	28111	28862	3	10	4000	4000	8000	28658	28729	1	1	61001	1000	1000	4004	5	0	0	4004	0	2	4	4000	4	8	4	1	0	13152	9279	6884	3199	11	55	19810	3225	3827	24	61	56	2	28222	15287	12432	14220	4000	28778	28703	28662	28667	28713
64004	28806	223	1	17	0	0	21	1	0	0	0	4	0	0	4924	28647	0	0	22786	4000	4000	4000	21634	9	17033	0	28202	28645	9	10	4000	4000	8000	28636	28699	1	1	61001	1000	1000	4005	5	8	0	4000	0	0	4	4000	4	8	4	2	0	13309	9546	6979	3210	12	58	19701	3205	3825	33	69	60	2	28162	15614	12376	14245	4000	28581	28674	28677	28773	28760
64004	28835	222	1	21	1	0	17	1	0	0	0	5	0	0	4716	28550	0	0	22603	4000	4000	4000	21637	8	17044	0	28175	28744	3	10	4000	4000	8000	28601	28655	1	1	61001	1000	1000	4005	5	8	1	4004	1	1	4	4002	4	0	4	0	0	13196	9478	6989	3152	12	67	19800	3212	3825	31	62	59	2	28240	15673	12463	14194	4000	28829	28723	28850	28721	28804
64005	28748	223	1	16	1	0	23	1	0	0	0	9	0	0	4690	28562	0	0	22608	4000	4000	4000	21628	6	17041	0	28063	28721	3	10	4000	4000	8000	28683	28609	1	1	61001	1000	1000	4005	5	8	1	4004	0	0	4	4002	6	8	4	2	0	13127	9584	7053	3232	9	57	19780	3349	3825	22	57	63	3	28190	15401	12644	13703	4000	28694	28746	28854	28850	28715

Count: 8

Code:

  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	160054	1241	1	0	1	0	1	0	0	0	0	108	0	2	160038	16	16	5	25	320100	100	320000	100	320000	500	7360028	0	0	160028	160054	160054	79990	3	80034	320100	200	320000	200	640000	160054	160051	1	1	80201	100	99	100	100	80000	80000	100	320014	14	0	0	0	320014	96	2	16	320002	16	44	14	0	0	0	0	5110	0	3	17	2	1	160044	320000	100	160055	160055	160048	160055	160064
320204	160054	1240	1	1	0	0	1	0	0	0	12	17	0	2	160039	0	0	1	25	320100	100	320000	100	320000	500	7360052	0	0	160029	160063	160054	79985	3	80036	320100	200	320000	200	640000	160052	160063	1	1	80201	100	99	100	100	80000	80000	100	320015	14	50	29	0	320016	101	0	28	320002	16	44	14	0	0	0	0	5112	0	2	26	2	1	160044	320000	100	160048	160055	160055	160055	160055
320204	160047	1241	1	1	0	0	1	2	0	0	21	17	0	2	160037	16	16	2	25	320100	100	320000	100	320000	500	7360460	0	0	160029	160052	160054	80069	3	80046	320100	200	320120	200	640000	160054	160052	1	1	80201	100	99	100	100	80000	80000	100	320014	14	44	0	0	320016	97	0	20	320002	14	44	14	1	0	0	0	5112	0	2	26	1	2	160044	320000	100	160055	160064	160064	160064	160048
320204	160063	1241	1	1	1	0	1	1	0	0	9	17	0	1	160036	16	16	1	25	320100	100	320060	100	320000	500	7360487	0	0	160029	160051	160055	79985	3	80045	320100	200	320000	200	640000	160054	160131	1	1	80201	100	99	100	100	80000	80000	100	320015	17	44	0	0	320016	102	1	18	320000	16	44	14	0	0	0	0	5112	0	2	17	1	2	160171	320000	100	160055	160055	160048	160055	160055
320204	160054	1241	1	1	0	0	1	0	0	0	0	14	1	1	160037	16	0	1	25	320160	100	320000	100	320000	500	7359692	0	0	160030	160054	160052	79989	3	80036	320100	200	320000	200	640000	160063	160054	1	1	80201	100	99	100	100	80000	80000	100	320015	15	0	0	1	320016	96	0	17	320000	16	0	14	1	0	0	0	5110	0	1	17	1	2	160180	320000	100	160137	160055	160055	160055	160053
320204	160054	1240	1	1	0	0	1	1	0	0	0	14	0	2	160039	16	16	0	25	320100	100	320000	100	320000	500	7360438	0	0	160029	160192	160047	79985	3	80029	320100	200	320000	200	640000	160054	160051	1	1	80201	100	99	100	100	80000	80000	100	320014	14	44	0	1	320016	96	1	17	320062	16	0	14	0	0	0	0	5112	0	2	17	1	3	160051	320000	100	160055	160048	160187	160055	160056
320204	160054	1240	1	1	0	0	1	1	0	0	144	17	0	1	160032	16	16	5	25	320100	100	320000	100	320000	500	7359884	0	0	160236	160053	160048	80001	15	80034	320100	200	320000	200	640000	160191	160054	1	1	80201	100	99	100	100	80000	80000	100	320014	14	44	0	1	320076	15	1	24	320002	16	44	14	1	0	0	0	5112	0	2	17	1	2	160060	320000	100	160064	160065	160064	160053	160086
320204	160054	1240	1	1	0	0	1	1	0	1	0	17	0	2	160036	16	0	2	25	320100	100	320000	100	320000	500	7360028	0	0	160022	160054	160047	80069	3	80029	320100	200	320000	200	640000	160052	160047	1	1	80201	100	99	100	100	80000	80000	100	320014	15	44	0	0	320016	111	1	21	320062	16	44	14	1	0	0	0	5112	0	3	17	1	2	160060	320000	100	160192	160053	160192	160191	160193
320204	160048	1241	1	0	0	0	0	2	2	2	396	283	0	2	160310	16	16	220	115	320282	100	320060	100	320432	511	7369652	0	0	160260	160460	160461	80145	27	80334	320316	202	320240	200	640720	160469	160607	4	1	80201	100	99	100	100	80000	80000	100	320194	14	51	0	0	320016	139	0	22	320002	14	44	14	0	0	0	0	5112	0	2	17	2	1	160044	320000	100	160055	160048	160055	160055	160048
320204	160054	1240	1	0	1	0	1	1	0	0	12	14	0	2	160037	16	16	32	25	320100	100	320000	100	320000	500	7359693	0	0	160029	160052	160063	79993	3	80034	320100	200	320000	200	640000	160054	160052	1	1	80201	100	99	100	100	80000	80000	100	320014	14	44	0	1	320016	110	0	16	320002	16	44	14	0	0	0	0	5112	0	2	17	2	2	160051	320000	100	160064	160064	160054	160065	160048

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	160180	1241	0	0	0	0	1	0	0	0	0	14	0	0	2	160027	16	16	0	25	320010	10	320000	10	320000	50	7359448	0	0	160018	160042	160044	79993	15	80129	320226	20	320120	20	640480	160321	160181	2	1	80021	10	9	10	10	80000	80000	10	320180	0	42	89	2	320196	0	0	23832	320122	2	42	0	0	5044	0	1	44	0	5	3	160408	1	320000	10	160320	160320	160320	160459	160596
320024	160458	1245	0	1	1	0	1	0	2	4	528	285	0	0	1	160027	16	0	1	25	320010	10	320000	10	320000	50	7359448	0	0	160015	160040	160043	79978	3	80024	320010	20	320000	20	640000	160043	160040	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320016	11	0	2	320002	2	44	14	0	5020	0	1	17	0	3	1	160039	0	320000	10	160043	160043	160043	160043	160055
320024	160043	1240	0	1	0	0	1	0	0	0	39	7	1	0	1	160025	16	16	0	25	320010	10	320000	10	320000	50	7359448	0	0	160017	160042	160042	79981	3	80024	320010	20	320000	20	640000	160042	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	0	2	320002	2	42	0	0	5020	0	1	17	0	2	1	160039	0	320000	10	160041	160041	160043	160044	160043
320024	160040	1241	0	0	0	0	1	0	0	0	6	0	1	0	0	160027	16	16	1	25	320010	10	320000	10	320000	50	7359448	0	0	160017	160042	160043	79992	3	80025	320010	20	320000	20	640000	160042	160040	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	0	2	320002	2	42	0	0	5022	0	4	17	0	2	1	160040	0	320000	10	160041	160043	160044	160043	160055
320024	160042	1241	0	0	0	0	1	0	0	0	0	3	0	0	0	160027	16	16	1	25	320010	10	320000	10	320000	50	7359352	0	0	160017	160042	160042	79980	3	80025	320010	20	320000	20	640000	160052	160063	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	2	16	320002	2	42	0	0	5022	0	2	17	0	3	1	160051	0	320000	10	160043	160041	160043	160043	160048
320024	160054	1241	0	1	0	0	0	0	0	0	0	14	0	0	1	160027	16	16	0	25	320010	10	320000	10	320000	50	7359448	0	0	160017	160042	160054	79981	3	80025	320010	20	320000	20	640000	160042	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	2	320016	0	2	2	320002	2	42	0	1	5020	0	1	17	0	2	1	160051	0	320000	10	160055	160044	160043	160044	160053
320024	160121	1241	0	1	0	0	1	0	0	0	0	17	0	0	1	160027	16	0	0	25	320010	10	320000	10	320000	50	7359352	0	0	160017	160042	160043	79981	3	80024	320010	20	320000	20	640000	160042	160043	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	0	2	320002	2	42	0	0	5020	5	2	17	0	2	2	160039	0	320000	10	160043	160043	160043	160043	160043
320024	160043	1241	0	0	0	0	0	0	0	0	0	3	0	0	0	160027	16	16	0	25	320010	10	320000	10	320000	50	7359448	0	0	160017	160042	160042	79980	20	80024	320010	20	320000	20	640000	160054	160040	1	1	80021	10	9	10	10	80000	80000	10	320183	0	42	118	2	320120	0	7	2387	320182	2	42	0	0	5412	0	4	323	0	2	1	160397	0	320000	10	160458	160598	160459	160457	160596
320024	160457	1243	0	1	1	0	0	1	3	4	396	190	0	0	0	160027	16	0	0	25	320010	10	320000	10	320000	50	7359352	0	0	160018	160042	160042	79981	3	80022	320010	20	320000	20	640000	160042	160043	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	59	2	320122	0	2	14	320000	14	42	0	0	5020	0	2	17	0	1	1	160039	0	320000	10	160055	160043	160044	160043	160043
320024	160042	1241	0	1	0	0	1	0	0	0	264	195	0	0	0	160027	0	16	0	25	320010	10	320000	10	320000	50	7359352	0	0	160015	160042	160042	79991	3	80022	320010	20	320000	20	640000	160054	160043	1	1	80021	10	9	10	10	80000	80000	10	320180	2	0	0	0	320002	0	0	14	320002	2	42	0	0	5022	0	1	17	0	3	1	160039	0	320000	10	160043	160043	160043	160044	160043

ST1 (multiple, 4 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations