Firestorm: ST1 (multiple, 4 regs, 1D) measurements

Code:

  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	1e	1f	22	23	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64006	29325	219	2	1	4	1	0	2	1	0	0	0	0	0	4475	28994	2	0	18099	4000	2000	2000	2000	2000	21800	16000	0	12	21833	28899	29177	3	10	4000	2000	2000	4000	4000	29193	29152	1	1	61001	1000	1000	2000	0	6	0	2000	0	0	0	2000	2	0	2	0	12881	9187	6899	3040	2	46	20303	3075	3808	13	45	45	28439	16522	13526	14893	2000	2000	29215	29222	29256	29158	29337
64004	29268	219	0	1	0	0	1	1	0	0	0	3	1	0	4498	29099	2	0	18070	4000	2000	2000	2000	2000	21802	16000	0	0	21847	28902	29237	3	10	4000	2000	2000	4000	4000	29111	29146	1	1	61001	1000	1000	2002	4	8	1	2002	0	0	2	2000	2	0	2	1	12754	9166	6804	3061	1	46	20215	3116	3817	18	50	45	28367	16216	13287	14879	2000	2000	29254	29209	29287	29254	29275
64004	29215	219	0	0	1	0	0	1	0	0	0	1	0	0	4504	29011	2	2	18001	4000	2000	2000	2000	2000	21805	16000	0	11	21892	28909	29232	3	10	4000	2000	2000	4000	4000	29153	29137	1	1	61001	1000	1000	2000	0	0	0	2000	0	0	0	2000	0	0	0	0	12864	9133	6824	3047	0	46	20241	3115	3804	16	48	47	28423	16333	13217	14777	2000	2000	29268	29304	29227	29310	29331
64004	29176	220	0	1	0	1	0	2	1	0	0	2	1	0	4522	29065	2	2	18054	4000	2000	2000	2000	2000	21806	16000	0	16	21826	28846	29260	3	10	4000	2000	2000	4000	4000	29123	29145	1	1	61001	1000	1000	2003	3	8	0	2002	0	1	5	2000	2	0	2	1	12859	8979	6826	3041	1	49	20207	3076	3802	15	52	52	28377	16301	13307	14878	2000	2000	29255	29234	29189	29297	29327
64004	29274	218	0	0	1	0	0	1	0	0	0	1	0	0	4604	29072	2	0	18060	4008	2000	2000	2000	2000	21814	16000	0	6	21850	28854	29312	3	10	4000	2000	2000	4000	4000	29227	29151	1	1	61001	1000	1000	2000	0	6	0	2000	0	0	0	2000	0	6	0	0	12724	9127	6801	3029	1	44	20238	3030	3817	12	48	42	28494	16415	13334	14995	2000	2000	29322	29305	29332	29292	29244
64004	29282	219	0	1	2	1	1	2	1	0	0	3	0	0	4460	29076	0	0	18037	4000	2000	2000	2000	2000	21810	16000	0	8	21909	28986	29223	3	10	4000	2000	2000	4000	4000	29244	29177	1	1	61001	1000	1000	2002	3	6	0	2002	0	0	5	2000	2	0	2	1	12988	9019	6814	3073	1	45	20299	3062	3810	14	47	44	28484	16552	13369	15007	2000	2000	29304	29250	29349	29324	29327
64004	29281	219	0	0	0	0	0	1	0	0	0	1	0	0	4578	29052	2	0	18049	4000	2000	2000	2000	2000	21811	16000	0	13	21849	28989	29246	3	10	4000	2000	2000	4000	4000	29208	29245	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	0	0	0	0	12843	9046	6820	3020	0	46	20311	3034	3812	12	52	49	28552	16525	13280	14735	2000	2000	29286	29283	29271	29292	29235
64004	29297	220	0	1	0	0	0	0	1	0	0	3	0	0	4700	29109	2	0	18106	4000	2000	2000	2000	2000	21809	16000	0	12	21900	28855	29237	3	10	4000	2000	2000	4000	4000	29202	29223	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	0	4	0	0	12937	9096	6809	3041	0	47	20253	3054	3810	17	44	49	28501	16351	13346	14842	2000	2000	29216	29359	29210	29310	29296
64004	29216	219	0	1	1	1	0	0	0	0	0	2	0	0	4532	29037	0	0	18036	4000	2000	2000	2000	2000	21801	16000	0	11	21857	29070	29174	3	10	4000	2000	2000	4000	4000	29233	29285	1	1	61001	1000	1000	2004	2	6	1	2002	1	0	2	2000	2	6	2	1	12837	9064	6836	3033	1	46	20285	3046	3805	15	41	55	28427	16427	13304	15087	2000	2000	29261	29267	29329	29384	29197
64004	29241	219	0	1	0	1	1	2	0	0	0	2	0	0	4572	29038	0	0	17970	4000	2000	2000	2000	2000	21811	16000	0	11	21842	28937	29215	3	10	4000	2000	2000	4000	4000	29227	29223	1	1	61001	1000	1000	2004	3	6	2	2002	1	2	8	2000	2	6	2	2	12809	9145	6847	3026	3	43	20210	3065	3814	8	50	48	28513	16370	13208	15025	2000	2000	29210	29254	29250	29264	29213

Count: 8

Code:

  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	23	37	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320206	80084	620	0	0	0	0	0	0	3	0	5827	80030	16	16	0	25	325364	100	165010	160000	100	160118	160108	500	2229366	1298626	0	80024	0	80045	80209	0	3	27	320100	200	160000	160000	200	320000	320960	80044	80045	1	1	80201	100	99	100	100	80000	80000	100	160062	0	34	0	0	160002	0	0	5	160002	2	34	0	5109	3	17	1	2	80042	160000	160000	100	80047	80049	80046	80046	80046
320204	80211	620	0	0	0	0	0	12	3	0	6104	80030	16	16	0	47	324864	100	164485	160000	100	160000	160000	500	2392843	1302442	0	80025	0	80045	80044	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	2	160002	2	34	0	5109	2	17	1	1	80042	160000	160000	100	80046	80050	80045	80047	80046
320204	80045	620	0	0	1	0	0	0	3	0	4062	80030	16	16	0	25	326510	100	164890	160000	100	160000	160000	500	2215712	1299352	0	80024	0	80045	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80211	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	0	160002	0	0	8	160002	2	34	0	5109	3	17	1	1	80042	160000	160000	100	80046	80046	80045	80047	80046
320204	80045	620	0	0	0	1	0	12	0	0	3983	80030	0	0	0	25	324925	100	165017	160000	100	160000	160000	500	2215406	1298997	0	80024	0	80049	80048	0	3	27	320326	200	160000	160000	200	320000	320000	80045	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160062	0	0	2	160002	2	34	0	5109	2	26	1	1	80041	160000	160000	100	80051	80046	80049	80046	80046
320204	80045	620	0	0	0	0	0	18	91	0	5336	80030	16	16	0	25	325610	100	167283	160000	100	160000	160000	500	2158486	1300833	0	80024	0	80044	80045	0	3	30	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	5	160002	2	34	0	5109	3	17	1	1	80042	160000	160000	100	80046	80046	80046	80047	80049
320204	80049	620	0	0	0	0	0	0	3	0	5626	80030	0	0	0	25	324973	100	168963	160060	100	160000	160000	500	2239656	1297826	0	80024	0	80045	80045	0	3	27	320100	200	160000	160000	200	320000	320960	80216	80048	2	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	8	160000	2	34	0	5109	2	17	1	1	80042	160000	160000	100	80046	80045	80050	80046	80046
320204	80045	620	0	0	0	0	0	0	9	0	4368	80030	16	0	0	25	326149	100	166080	160000	100	160000	160108	500	2078237	1304383	0	80024	0	80045	80045	0	3	27	320100	200	160000	160120	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	5	160002	0	34	0	5109	3	17	1	1	80042	160000	160000	100	80046	80050	80046	80046	80046
320204	80045	621	0	0	0	0	0	0	3	1	3909	80033	16	0	0	25	324178	100	164844	160000	100	160000	160000	500	2228088	1299006	0	80024	0	80046	80044	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	5	160002	2	34	0	5109	3	17	1	1	80045	160000	160000	100	80046	80049	80044	80046	80046
320204	80049	622	0	0	0	0	0	0	3	0	3982	80030	16	16	0	25	326247	100	165461	160000	100	160000	160000	500	2158849	1299612	0	80024	0	80045	80045	0	3	30	320100	200	160000	160000	200	320000	320000	80045	80045	2	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	2	160002	2	34	0	5109	3	26	3	1	80195	160000	160000	100	80210	80376	80087	80149	80376
320204	80212	621	0	0	0	1	2	132	179	0	3526	80196	16	16	89	47	323278	100	165144	160060	100	160118	160108	511	2204692	1300463	0	80418	0	80211	80378	163	9	123	320326	202	160240	160120	200	320480	320480	80218	80373	3	1	80201	100	99	100	100	80000	80000	100	161020	0	34	871	0	160902	0	0	927	160122	2	34	7	5135	5	26	1	3	80196	160000	160000	100	80375	80210	80376	80220	80211

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320026	80060	620	1	0	0	0	0	0	12	9	0	0	5733	0	80043	16	16	0	25	328066	10	165327	160000	10	160000	160000	50	2390491	1300862	0	80024	80045	80045	0	3	26	320010	20	160000	160000	20	320000	320000	80049	80048	2	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160002	0	0	2	160002	16	34	14	0	0	5019	8	17	6	8	80058	160000	160000	10	80062	80046	80059	80059	80046
320024	80051	620	1	1	0	1	0	0	144	21	0	0	2169	1	80029	16	16	1	25	329014	10	166787	160000	10	160000	160000	50	3679304	1299785	0	80196	80058	80059	0	3	40	320010	20	160000	160000	20	320000	320000	80222	80052	1	1	80021	10	9	10	10	80000	80000	10	160015	14	36	0	0	160016	0	0	21	160002	16	40	14	0	0	5019	6	17	8	8	80055	160000	160000	10	80046	80050	80046	80058	80052
320024	80060	620	1	0	0	0	0	0	6	20	0	0	5086	0	80035	16	16	0	25	325703	10	160007	160000	10	160000	160000	50	3679360	1298361	0	80024	80051	80051	0	3	39	320010	20	160000	160000	20	320000	320000	80050	80051	1	1	80021	10	9	10	10	80000	80000	10	160015	14	34	0	0	160002	1	1	17	160002	16	38	14	0	0	5019	8	17	8	7	80049	160000	160000	10	80211	80059	80046	80060	80060
320024	80059	620	1	0	0	1	0	0	0	3	0	0	5536	1	80036	16	16	0	25	325059	10	164843	160000	10	160118	160000	50	2399920	1301575	0	80024	80058	80059	0	3	31	320010	20	160000	160000	20	320000	320000	80051	80044	1	1	80021	10	9	10	10	80000	80000	10	160014	0	34	0	0	160016	0	0	17	160000	16	36	0	0	0	5019	6	17	9	6	80047	160000	160000	10	80046	80049	80053	80046	80061
320024	80058	622	1	1	1	0	0	2	18	21	1	0	5237	0	80037	16	16	0	25	325485	10	165640	160000	10	160000	160000	50	2158912	1299474	0	80024	80045	80044	0	6	26	320010	20	160000	160000	20	320000	320000	80048	80048	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160002	0	0	917	160002	2	34	0	0	0	5019	10	17	6	9	80047	160000	160000	10	80046	80050	80051	80060	80051
320024	80049	621	1	0	0	1	0	0	0	20	0	0	4510	0	80035	0	16	0	25	325175	10	165779	160000	10	160000	160108	50	2319900	1299785	0	80025	80049	80060	82	3	40	320010	20	160000	160000	20	320000	320000	80049	80050	1	1	80021	10	9	10	10	80000	80000	10	160122	0	34	0	0	160002	0	0	2	160002	2	34	0	0	0	5019	7	17	8	8	80045	160000	160000	10	80050	80046	80046	80046	80046
320024	80211	620	0	0	0	0	0	0	12	3	0	0	3571	1	80034	16	16	0	25	323396	10	160980	160000	10	160118	160000	50	2223170	1304898	0	80025	80045	80052	0	3	27	320010	20	160000	160000	20	320000	320000	80060	80059	1	1	80021	10	9	10	10	80000	80000	10	160014	14	34	0	1	160016	1	1	927	160002	16	34	14	0	0	5019	7	26	10	7	80213	160000	160000	10	80219	80212	80212	80218	80046
320024	80137	622	0	1	1	0	1	1	264	91	0	0	4374	0	80194	16	16	274	70	326312	10	164461	160060	10	160118	160108	50	2258495	1306765	0	80336	80211	80374	83	8	218	320462	20	160360	160120	20	320480	320240	80210	80211	2	1	80021	10	9	10	10	80000	80000	10	160000	17	0	129	0	160076	0	0	1857	160122	2	36	14	0	0	5046	7	26	9	7	80215	160000	160000	10	80211	80378	80230	80385	80558
320024	80220	623	1	2	0	0	0	0	12	19	0	0	5079	1	80030	14	16	0	25	324607	10	164177	160000	10	160000	160000	50	2398651	1297498	0	80024	80049	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80044	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	1	160004	0	0	18	160002	2	34	0	0	0	5019	7	17	8	6	80045	160000	160000	10	80046	80046	80046	80046	80046
320024	80045	621	0	0	0	0	0	0	0	0	0	0	6006	0	80030	16	16	0	25	327585	10	166183	160000	10	160000	160000	50	2226226	1295822	0	80025	80045	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80048	80050	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	8	160002	2	36	0	0	0	5019	8	17	6	6	80041	160000	160000	10	80046	80046	80046	80047	80046

ST1 (multiple, 4 regs, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations