Firestorm: ST1 (multiple, 4 regs, 2D) measurements

Code:

  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	1e	1f	22	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
64005	29266	218	1	19	0	1	15	1	0	0	1	0	4587	29030	0	0	23140	4000	4000	4000	21605	5	17028	28368	29254	3	10	4000	4000	8000	29085	29102	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	0	4000	0	12	0	0	0	12699	9167	6827	3041	9	36	20264	3075	3813	10	38	36	28449	16436	13289	15159	4000	29300	29282	29184	29193	29323
64004	29239	219	0	15	0	0	15	0	0	0	1	0	4645	29149	0	0	23205	4000	4000	4000	21619	3	17028	28365	29287	3	10	4000	4000	8000	29076	29103	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4000	0	8	0	0	0	12908	9282	6845	3044	8	34	20291	3101	3812	5	31	36	28347	16296	13279	14966	4000	29198	29257	29288	29281	29271
64004	29239	219	0	18	0	0	21	0	0	0	1	0	4578	29081	0	0	23154	4000	4000	4000	21615	5	17042	28365	29252	3	10	4000	4000	8000	29158	29091	1	1	61001	1000	1000	4000	0	8	0	4000	2	0	0	4000	0	8	0	0	207	13250	9495	6957	3126	11	44	20380	3332	3812	6	39	45	28771	16176	13297	15138	4000	29272	29266	29235	29509	29207
64004	29285	219	0	16	0	0	19	0	0	0	1	0	4547	29140	0	0	23156	4000	4000	4000	21609	5	17023	28406	29217	3	10	4000	4000	8000	29152	29110	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4000	0	8	0	0	0	13152	9106	6843	3078	7	40	20212	3082	3818	11	39	40	28454	16268	13235	14867	4000	29443	29302	29326	29300	29204
64004	29268	219	0	17	0	0	16	0	0	0	1	0	4591	29079	0	0	23079	4000	4000	4000	21622	7	17029	28406	29150	3	10	4000	4000	8000	29137	29012	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	0	4000	0	8	0	0	0	12897	9213	6808	3093	12	40	20374	3129	3808	10	43	38	28352	16259	13359	14848	4000	29266	29312	29283	29325	29296
64004	29236	219	1	15	0	0	16	0	0	6	5	0	4667	29134	0	0	23164	4000	4000	4000	21607	2	17043	28428	29269	3	10	4000	4000	8000	29098	29188	1	1	61001	1000	1000	4006	5	12	1	4004	0	1	4	4000	4	16	4	0	0	12897	9173	6854	3097	9	33	20279	3079	3814	6	41	39	28385	16391	12965	15192	4000	29297	29303	29273	29297	29177
64004	29274	220	1	14	1	0	15	1	0	0	5	0	4660	29120	0	0	23230	4000	4000	4000	21621	3	17019	28454	29245	3	10	4000	4000	8000	29153	29260	1	1	61001	1000	1000	4004	5	16	1	4004	0	2	4	4000	4	8	4	1	0	12872	9214	6881	3031	8	35	20219	3092	3812	12	37	43	28369	16148	13382	15086	4000	29281	29270	29294	29273	29243
64004	29291	219	0	15	0	0	18	0	0	0	1	0	4670	29090	4	0	23185	4000	4000	4000	21621	5	17011	28434	29227	3	10	4000	4000	8000	29118	29169	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4000	0	8	0	0	0	12779	9070	6831	3077	7	43	20279	3064	3814	6	40	39	28406	16350	12975	14980	4000	29266	29273	29219	29270	29242
64004	29235	220	0	16	0	0	15	0	0	0	1	0	4488	29009	0	0	23222	4000	4000	4000	21622	5	17050	28358	29277	3	10	4000	4000	8000	29131	29184	1	1	61001	1000	1000	4004	5	12	2	4004	0	2	4	4002	4	8	4	1	0	12926	9082	6853	3044	11	39	20311	3088	3815	8	34	44	28376	16162	13282	14844	4000	29295	29306	29374	29317	29254
64004	29251	219	0	23	0	0	15	0	0	0	1	0	4647	29039	0	0	23141	4000	4000	4000	21610	5	17040	28405	29257	3	10	4000	4000	8000	29144	29133	1	1	61001	1000	1000	4005	5	8	2	4004	0	0	4	4000	4	8	4	1	0	12799	9194	6879	3037	10	42	20269	3082	3816	7	39	39	28440	16376	13280	14727	4000	29341	29279	29195	29339	29230

Count: 8

Code:

  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	160053	1240	0	0	0	0	0	0	0	0	0	0	1	160027	16	16	1	25	320100	100	0	320000	100	320011	500	7359863	0	160094	0	160120	160042	79985	7	80016	320111	200	320020	200	640040	160040	160040	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320000	0	0	5	320002	0	0	2	34	0	1	1	1	5119	1	16	1	1	160046	0	320000	100	160050	160051	160052	160050	160043
320204	160045	1240	1	0	0	1	0	0	0	0	3	0	0	160035	0	16	3	25	320100	100	0	320000	100	320000	500	7359424	0	160017	0	160042	160040	79980	3	80024	320100	200	320000	200	640000	160042	160050	1	1	80201	100	99	100	100	80000	80000	100	320000	0	36	0	0	320002	0	0	18	320002	0	0	2	34	0	0	0	0	5110	1	17	2	1	160039	0	320000	100	160043	160050	160051	160051	160043
320204	160042	1240	0	0	0	1	0	0	0	0	3	0	1	160027	16	16	0	25	320100	100	0	320000	100	320000	500	7359424	0	160024	0	160040	160042	79980	3	80024	320100	200	320000	200	640000	160120	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	0	0	2	320002	16	405	2	34	0	1	0	0	5110	2	17	1	1	160037	0	320000	100	160043	160041	160043	160043	160051
320204	160050	1241	1	0	0	0	0	0	0	0	9	0	1	160027	16	16	2	25	320100	100	0	320000	100	320000	500	7359424	0	160017	0	160050	160120	79978	3	80024	320100	200	320000	200	640000	160042	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320002	1	0	2	320002	0	0	2	34	0	0	0	0	5112	1	17	2	2	160051	0	320000	100	160114	160043	160043	160043	160043
320204	160042	1240	0	0	0	1	0	0	0	0	3	0	0	160027	16	0	0	25	320100	100	0	320000	100	320000	500	7359424	0	160015	0	160050	160042	79980	3	80024	320100	200	320000	200	640000	160042	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	0	0	2	320002	0	0	0	34	0	0	0	0	5112	2	17	2	2	160117	0	320000	100	160043	160043	160043	160043	160043
320204	160042	1240	1	0	0	1	0	0	0	0	3	0	1	160027	16	16	35	295	322502	100	1	320000	100	322346	500	7359352	0	160017	3	160050	160120	79980	3	80031	320100	200	320000	200	640000	160049	160040	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320000	0	0	113	320002	0	0	2	34	0	0	0	0	5112	2	17	2	1	160046	0	320000	100	160041	160041	160043	160041	160043
320204	160042	1285	1	0	0	1	0	0	0	12	6	0	1	160036	16	16	0	25	320100	100	0	320000	100	320000	500	7359352	0	160390	0	160434	160042	84526	3	80377	320208	200	320000	200	640280	160042	160127	3	1	80201	100	99	100	100	80000	80000	100	320000	0	34	28	0	320002	0	0	14	320002	0	0	2	34	0	0	0	0	5112	2	17	2	1	160037	0	320000	100	160041	160043	160043	160043	160043
320204	160042	1241	0	0	0	1	0	0	0	0	3	0	1	160035	16	16	0	25	320100	100	0	320000	100	320000	500	7359856	1	160024	0	160049	160042	79980	3	80025	320100	200	320000	200	640000	160042	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	36	0	0	320002	1	0	33	320002	0	0	2	34	0	0	0	0	5110	2	17	2	1	160039	0	320000	100	160043	160043	160043	160043	160051
320204	160059	1240	1	0	0	1	1	0	0	12	6	0	1	160025	16	16	0	25	320100	100	0	320000	100	320000	500	7359424	0	160017	0	160042	160042	80057	3	80024	320100	200	320120	200	640000	160040	160040	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320000	0	0	2	320002	0	0	2	34	0	0	0	0	5130	2	17	2	2	160039	0	320000	100	160043	160043	160041	160181	160043
320204	160042	1241	0	0	0	0	0	0	0	132	9	0	0	160027	16	0	74	25	320100	100	0	320000	100	320000	500	7359424	0	160142	0	160049	160040	79980	15	80024	320100	200	320000	200	640000	160042	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	0	0	20	320002	0	0	4	34	0	0	0	0	5112	1	17	1	1	160039	0	320000	100	160043	160043	160043	160044	160051

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	160043	1241	0	0	0	0	0	0	0	3	0	0	0	160027	0	16	16	1	25	320010	10	320000	10	320000	50	7359448	160017	160040	160043	79981	3	80036	320010	20	320000	20	640000	160042	160046	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	0	2	320002	2	44	0	0	5020	0	14	17	5	13	160039	0	320000	10	160043	160043	160044	160043	160043
320024	160042	1240	0	0	0	0	0	0	0	3	0	0	0	160028	0	16	0	1	25	320010	10	320000	10	320000	50	7360000	160017	160042	160040	79980	3	80024	320010	20	320000	20	640000	160043	160048	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	0	2	320002	0	42	0	0	5020	0	5	17	13	12	160039	0	320000	10	160044	160043	160043	160044	160182
320024	160040	1241	0	0	0	0	1	0	0	3	0	0	0	160027	0	16	16	1	25	320010	10	320000	10	320000	50	7359448	160018	160042	160042	79980	3	80024	320010	20	320120	20	640000	160040	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	0	0	320000	0	0	2	320062	0	0	0	0	5020	0	14	17	13	12	160037	0	320000	10	160043	160043	160043	160043	160043
320024	160043	1240	0	0	0	0	0	0	0	3	0	0	0	160027	0	16	16	1	25	320010	10	320000	10	320000	50	7359448	160017	160042	160043	79981	3	80025	320010	20	320000	20	640000	160042	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	0	0	320002	0	0	2	320002	2	42	0	0	5020	0	5	17	12	12	160040	0	320000	10	160182	160043	160043	160043	160043
320024	160181	1241	0	0	0	0	0	0	0	3	0	0	0	160028	0	16	16	1	25	320070	10	320000	10	320000	50	7364284	160017	160043	160043	79981	3	80025	320010	20	320000	20	642880	166270	160053	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320000	1	0	2	320002	2	42	0	0	5020	0	7	17	12	13	160039	0	320000	10	160043	160043	160043	160043	160182
320024	160180	1285	0	0	0	0	0	0	12	3	0	0	0	160166	0	16	16	0	25	320010	10	320000	10	320108	50	7359448	160018	160042	160042	79981	3	80024	320010	20	320000	20	640000	160042	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	0	2	320002	2	44	0	0	5020	0	14	17	12	12	160039	0	320000	10	160043	160043	160043	160044	160044
320024	160042	1286	0	0	0	0	0	0	0	3	0	0	0	160039	0	16	16	0	25	320070	10	320000	10	320000	50	7359352	160018	160040	160042	79980	3	80036	320118	20	320000	20	640000	160043	160085	2	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	0	2	320002	2	44	0	0	5020	0	5	17	12	7	160051	0	320000	10	160182	160044	160043	160043	160043
320024	160180	1286	0	0	0	0	0	0	9	3	0	0	0	160027	0	16	16	1	25	320010	10	320000	10	320000	50	7364236	160017	160042	160042	79978	3	80024	320010	20	320000	20	640000	160043	160046	1	1	80021	10	9	10	10	80000	80000	10	320060	0	42	29	2	320062	0	0	811	320062	2	42	2	0	5448	0	14	44	13	13	160277	0	320000	10	160449	160324	160460	160457	160598
320024	160455	1289	4	1	0	0	2	4	264	267	0	0	0	160442	0	16	16	1	25	320010	10	320000	10	320000	50	7359472	160017	160042	160043	79981	3	80025	320010	20	320000	20	640000	160042	160046	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	0	2	320002	2	42	0	0	5020	0	12	17	10	6	160040	0	320000	10	160044	160043	160043	160043	160044
320024	160042	1285	0	0	0	0	0	0	0	3	0	0	0	160025	0	16	16	0	25	320010	10	320000	10	320000	50	7359448	160017	160042	160042	79980	3	80022	320010	20	320000	20	640000	160040	160043	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	0	0	320002	2	42	0	0	5020	0	12	17	14	15	160039	0	320000	10	160044	160043	160043	160043	160043

ST1 (multiple, 4 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations