Firestorm: ST1 (multiple, 4 regs, 2S) measurements

Code:

  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0f	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64006	29366	227	1	1	2	1	0	3	1	0	0	0	3	0	0	0	4823	29158	0	2	18207	4000	2000	2000	2000	2000	21807	16000	12	21910	29059	29355	3	10	4000	2000	2000	4000	4000	29199	29296	1	1	61001	1000	1000	2002	2	4	1	2002	0	1	2	2000	2	4	2	1	0	13339	9288	6918	3179	0	48	20340	3191	3809	18	49	49	28660	16067	13227	14895	2000	2000	29340	29292	29387	29267	29439
64004	29543	229	0	1	1	0	0	0	1	0	0	0	3	0	0	0	4707	29206	0	0	18296	4000	2000	2000	2000	2000	21807	16000	10	21895	29056	29248	3	10	4000	2000	2000	4000	4000	29292	29251	1	1	61001	1000	1000	2003	4	6	0	2002	0	1	2	2000	2	4	2	1	0	13230	8942	6731	2984	2	55	20296	3289	3812	32	54	47	28422	15950	12982	14524	2000	2000	29126	29064	29122	29169	29170
64004	29104	233	0	1	1	1	1	1	0	0	0	6	5	0	0	0	4650	28856	2	2	17847	4000	2000	2000	2002	2000	21797	16000	8	21920	28908	29234	3	10	4000	2000	2000	4000	4000	29503	29465	1	1	61001	1000	1000	2002	3	0	0	2002	0	2	2	2000	2	6	2	3	0	13455	9322	6961	3202	0	49	20412	3303	3808	19	46	57	28781	16399	13305	14641	2000	2000	29515	29519	29494	29654	29441
64004	29538	237	0	1	0	0	0	0	0	0	2	0	3	0	0	0	4749	29298	0	0	18654	4000	2000	2000	2000	2000	21812	16000	6	21936	29223	29772	6	10	4000	2000	2000	4000	4000	29425	29347	1	1	61001	1000	1000	2004	2	0	1	2002	0	6	2	2000	2	6	2	1	0	13018	9383	6929	3148	1	47	20399	3184	3816	17	45	51	28693	15881	13365	14944	2000	2000	29424	29377	29319	29424	29389
64004	29379	227	0	1	2	2	0	1	0	0	0	0	3	0	0	1	4558	29176	2	0	18225	4000	2000	2000	2000	2000	21878	16000	5	21912	29156	29295	3	30	4000	2000	2000	4000	4000	29154	29380	1	1	61001	1000	1000	2002	3	4	1	2002	0	2	397	2000	2	6	2	2	0	13295	9271	6972	3085	0	47	20361	3238	3813	14	40	42	28807	16147	13379	14857	2000	2000	29575	29391	29450	29400	29362
64004	29393	227	0	1	0	2	0	0	1	0	0	0	3	0	0	0	4666	29265	0	0	18219	4000	2000	2000	2000	2000	21820	16000	4	21939	29134	29421	3	29	4000	2000	2000	4000	4000	29253	29392	1	1	61001	1000	1000	2003	3	6	1	2002	0	1	392	2000	2	6	2	1	0	13179	9333	7002	3119	1	49	20403	3264	3813	18	54	49	28678	16259	13197	14767	2000	2000	29440	29446	29343	29336	29367
64004	29572	228	2	1	0	1	0	0	1	0	0	12	3	0	0	0	4708	29191	0	0	18196	4000	2000	2000	2000	2002	21807	16000	5	21926	29204	29342	3	10	4000	2000	2000	4000	4000	29371	29305	1	1	61001	1000	1000	2002	3	6	0	2002	0	6	2	2000	2	6	2	1	0	13256	9406	6970	3160	1	46	20422	3262	3817	16	48	43	28734	16316	13286	14664	2000	2000	29430	29444	29348	29364	29400
64004	29420	227	0	1	0	1	0	1	1	0	0	6	2	0	0	0	4612	29139	0	0	18286	4000	2000	2000	2000	2000	21801	16000	1	21946	29059	29437	3	10	4000	2000	2000	4000	4000	29397	29366	1	1	61001	1000	1000	2002	3	6	0	2002	0	1	2	2000	2	6	2	1	0	13323	9469	6885	3148	1	47	20402	3277	3814	16	43	47	28733	16266	13237	15007	2000	2000	29346	29421	29302	29453	29513
64004	29549	228	0	1	0	0	0	0	2	2	1	9	3	0	0	0	4618	29174	0	0	18332	4000	2000	2000	2000	2000	21807	16000	2	21885	29158	29323	3	10	4000	2000	2000	4000	4000	29331	29343	1	1	61001	1000	1000	2002	3	4	1	2002	8	0	5	2000	2	4	2	1	0	13474	9500	6938	3182	0	45	20472	3414	3817	10	44	51	28630	16211	13425	14569	2000	2000	29365	29292	29349	29325	29424
64004	29464	228	0	1	1	0	0	0	0	0	0	0	3	0	0	0	4626	29168	0	0	18189	4000	2000	2000	2000	2000	21802	16000	4	21944	28999	29338	3	10	4000	2000	2000	4000	4000	29232	29172	1	1	61001	1000	1000	2002	2	6	1	2002	0	1	2	2000	2	4	2	1	0	12975	9167	6948	3036	1	47	20357	3239	3817	15	46	51	28683	16238	13469	14754	2000	2000	29307	29248	29270	29303	29262

Count: 8

Code:

  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320206	80071	620	0	0	0	0	0	0	0	3	0	0	3819	1	80031	16	16	0	25	324474	100	166182	160000	100	160000	160000	500	2234338	1309774	0	1	80024	80045	80045	0	3	32	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	2	160000	2	34	0	0	0	0	5109	1	17	2	2	80046	0	160000	160000	100	80046	80050	80046	80046	80050
320204	80045	620	0	0	1	0	0	0	0	9	0	0	5201	1	80030	0	16	0	25	325433	100	163890	160000	100	160000	160000	500	2239682	1298117	0	1	80024	80045	80044	0	3	27	320100	200	160000	160000	200	320240	320000	80048	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160000	0	0	2	160002	2	34	0	0	0	0	5109	1	17	2	2	80042	0	160000	160000	100	80046	80046	80045	80049	80044
320204	80045	620	1	0	1	0	0	0	0	6	0	0	6152	1	80030	16	16	0	25	326514	100	164226	160000	100	160000	160000	500	2158853	1300647	0	1	80023	80043	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80049	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	1	0	5	160002	2	34	0	0	0	0	5111	1	17	1	1	80045	0	160000	160000	100	80046	80046	80046	80046	80049
320204	80049	620	0	0	1	0	0	0	0	3	1	0	6118	0	80030	16	16	0	25	324000	100	166470	160000	100	160000	160000	500	2398606	1299644	0	1	80024	80045	80044	0	3	26	320100	200	160000	160000	200	320000	320000	80049	80048	1	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	0	160002	0	0	2	160002	0	34	0	0	0	0	5111	2	17	2	1	80042	0	160000	160000	100	80046	80049	80046	80046	80046
320204	80048	620	0	0	0	0	0	0	561	355	0	0	6977	1	80036	16	16	0	25	324384	100	165860	160000	100	160000	160000	500	2112562	1294694	0	1	80024	84223	83163	0	17	728	320552	200	160600	160000	200	320000	320272	80048	80048	1	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	0	160000	0	0	0	160002	2	34	0	0	0	0	5109	1	17	1	1	80042	0	160000	160000	100	80050	80046	80046	80046	80046
320204	80045	620	1	0	1	0	0	0	0	0	0	0	4212	1	80034	0	16	0	25	325684	100	163221	160000	100	160000	160000	500	2158495	1293147	0	1	80024	80049	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	8	160002	2	34	0	0	0	0	5111	2	17	2	2	80042	0	160000	160000	100	80046	80050	80468	80048	80046
320204	80049	599	1	0	1	0	0	0	0	3	0	0	5000	1	80030	16	16	0	25	325080	100	164967	160072	16656	163422	160648	500	2395199	1290952	0	1	80024	83477	85146	0	33	133	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	55	0	8	160000	2	34	0	0	0	0	5111	1	17	2	2	80042	0	160000	160000	100	80046	80046	80046	80050	80046
320204	80045	599	0	0	1	0	0	0	0	3	0	0	6164	0	80034	16	16	0	25	326291	100	163447	160000	100	160000	160000	500	2230983	1298614	0	1	80024	80045	80045	0	3	30	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	0	160000	0	0	186	160002	2	0	0	0	0	0	5109	1	17	1	2	80046	0	160000	160000	100	80045	80050	80046	80045	80050
320204	80044	600	1	0	1	0	0	0	0	3	0	0	6800	1	80034	16	16	0	26	325559	100	164228	160004	100	160134	160016	500	2077408	1295227	0	1	80024	80045	80045	0	13	16	320132	200	160016	160016	200	320032	320032	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	0	160002	0	0	12	160002	2	0	0	1	1	1	5116	0	16	2	1	80043	0	160000	160000	100	80046	80046	80046	80047	80046
320204	80045	600	1	0	0	0	0	0	0	3	0	0	6176	1	80030	16	16	0	25	325403	100	163899	160000	100	160000	160000	500	2206840	1304612	3	1	80024	80045	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80046	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	0	160002	2	42	0	0	0	0	5111	2	17	2	1	80042	0	160000	160000	100	80046	80046	80046	80046	80046

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320026	80056	621	1	0	1	0	0	0	19	0	0	5463	1	80037	16	16	0	25	325185	10	165098	160000	10	160000	160000	50	2559888	1303504	80024	80052	80052	0	3	32	320010	20	160000	160000	20	320000	320000	80051	80053	1	1	80021	10	9	10	10	80000	80000	10	160015	14	44	0	0	160016	1	2	17	160002	2	42	14	0	5019	9	17	8	9	80048	160000	160000	10	80053	80053	80051	80052	80052
320024	80230	620	1	0	1	0	0	0	18	0	0	4739	1	80036	16	16	0	25	324965	10	166081	160000	10	160000	160000	50	2719801	1304015	80026	80063	80045	0	3	33	320010	20	160000	160000	20	320000	320000	80052	80046	1	1	80021	10	9	10	10	80000	80000	10	160014	14	44	0	0	160016	0	0	16	160002	16	44	14	0	5019	8	17	9	8	80049	160000	160000	10	80052	80053	80046	80052	80052
320024	80053	620	1	0	0	2	0	0	106	0	0	4820	1	80208	16	16	187	69	323651	10	166352	160060	10	160354	160108	50	2250114	1293298	80337	80384	82386	1332	14	228	320236	20	160120	160120	20	320480	320480	80211	80220	2	1	80021	10	9	10	10	80000	80000	10	160134	14	42	63	0	160076	0	0	938	160122	16	44	14	0	5047	9	26	10	11	82816	160000	160000	10	80223	80221	80224	80221	80222
320024	80224	622	1	2	2	2	1	264	105	0	0	4858	0	80196	16	16	101	137	323354	10	163940	160060	10	160236	160108	50	2294719	1297041	80026	80050	80051	0	3	33	320462	20	160000	160000	20	320000	320000	80063	80051	1	1	80021	10	9	10	10	80000	80000	10	160015	15	44	4	0	160016	0	0	17	160002	16	44	14	0	5019	8	17	8	10	80050	160000	160000	10	80052	80052	80052	80198	80053
320024	80052	620	1	0	1	0	0	0	17	0	0	5887	1	80037	16	16	0	25	325692	10	164650	160000	10	160000	160000	50	2559734	1313758	80027	80053	80051	0	3	32	320010	20	160000	160000	20	320000	320000	80052	80045	1	1	80021	10	9	10	10	80000	80000	10	160015	14	44	0	0	160016	0	0	19	160002	16	42	14	0	5019	9	17	9	4	80060	160000	160000	10	80052	80052	80051	80056	80051
320024	80051	621	1	1	0	0	0	0	17	0	0	4470	1	80035	16	16	0	25	324877	10	165752	160000	10	160000	160000	50	2719433	1302357	80026	80051	80051	0	3	45	320010	20	160000	160000	20	320000	320000	80051	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	14	44	7	0	160016	0	0	21	160002	16	44	14	1	5019	8	17	8	10	80049	160000	160000	10	80051	80046	80053	80052	80052
320024	80052	620	1	1	0	0	0	3	18	0	0	5598	1	80036	16	16	0	25	325215	10	165260	160000	10	160000	160000	50	2799763	1298821	80024	80052	80051	0	3	34	320010	20	160000	160000	20	320000	320000	80052	80052	1	1	80021	10	9	10	10	80000	80000	10	160015	14	42	0	0	160016	0	0	16	160002	16	44	14	0	5019	10	17	6	8	80048	160000	160000	10	80052	80052	80063	80066	80053
320024	80063	621	1	0	0	0	0	0	17	1	0	4708	1	80036	16	16	0	25	326958	10	165939	160000	10	160000	160000	50	2559849	1298250	80027	80052	80051	0	3	34	320010	20	160000	160000	20	320000	320000	80052	80045	1	1	80021	10	9	10	10	80000	80000	10	160015	14	44	0	0	160016	0	1	16	160002	16	44	14	0	5019	8	17	10	10	80052	160000	160000	10	80052	80052	80053	80052	80052
320024	80050	621	1	1	0	0	0	12	3	0	0	7053	1	80048	16	16	0	25	324222	10	164275	160000	10	160000	160000	50	2638483	1329299	80027	80051	80051	0	9	34	320010	20	160000	160000	20	320000	320000	80053	80052	1	1	80021	10	9	10	10	80000	80000	10	160014	14	44	0	0	160016	0	0	2	160002	16	44	14	0	5019	8	17	6	8	80048	160000	160000	10	80063	80053	80054	80053	80064
320024	80051	621	1	0	0	0	0	12	17	0	0	5367	1	80038	16	16	0	25	328228	10	166955	160000	10	160000	160000	50	2719163	1293624	80026	80050	80045	0	3	32	320010	20	160000	160000	20	320000	320000	80044	80051	1	1	80021	10	9	10	10	80000	80000	10	160015	14	44	0	0	160002	0	1	17	160002	16	44	14	0	5019	7	17	9	9	80048	160000	160000	10	80046	80052	80052	80052	80046

ST1 (multiple, 4 regs, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations