Firestorm: ST1 (multiple, 4 regs, 4H) measurements

Code:

  st1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64006	28765	223	2	10	0	8	0	0	0	0	0	1	0	0	4809	28608	2	2	17409	4000	2000	2000	2000	2000	21802	16000	12	1	0	21872	28462	28607	3	10	4000	2000	2000	4000	4000	28612	28561	1	1	61001	1000	1000	0	2000	0	6	0	2002	10	0	11	2002	2	6	0	0	13401	9688	6928	3262	2	42	19540	3120	3803	19	41	45	28041	15440	12380	14031	2000	2000	28568	28586	28516	28653	28554
64004	28635	221	1	9	0	1	0	0	0	0	3	0	0	0	4733	28476	2	0	17399	4000	2000	2000	2000	2000	21810	16000	26	0	0	21928	28381	28583	3	10	4000	2000	2000	4000	4000	28501	28552	1	1	61001	1000	1000	0	2000	0	6	0	2002	25	0	5	2002	0	0	0	0	13205	9801	7001	3162	2	44	19609	3206	3809	17	38	47	28221	15298	12476	13732	2000	2000	28502	28446	28386	28630	28595
64004	28468	221	0	8	0	8	0	0	0	0	3	0	0	0	4776	28536	2	2	17544	4000	2000	2000	2000	2000	21812	16000	20	0	8	21914	28359	28632	3	10	4000	2000	2000	4000	4000	28509	28662	1	1	61001	1000	1000	0	2002	0	0	0	2002	12	0	9	2002	0	6	0	0	13367	9372	6981	3247	4	42	19704	3154	3809	13	41	48	28111	15043	12662	13665	2000	2000	28556	28606	28602	28548	28701
64004	28574	223	0	12	0	7	0	0	0	12	0	1	0	0	4758	28434	2	2	17601	4000	2000	2000	2000	2000	21816	16000	20	0	0	21896	28327	28573	3	10	4000	2000	2000	4000	4000	28677	28561	1	1	61001	1000	1000	0	2000	0	0	0	2002	48	0	2	2002	0	0	0	0	13460	9658	7031	3208	1	44	19590	3219	3814	20	45	49	28160	15347	12676	13852	2000	2000	28660	28630	28520	28547	28646
64004	28674	221	0	8	0	5	0	0	0	0	3	0	0	0	4729	28596	2	2	17408	4000	2000	2000	2000	2000	21812	16000	23	0	0	21837	28409	28662	3	10	4000	2000	2000	4000	4000	28557	28537	1	1	61001	1000	1000	0	2000	0	0	0	2002	59	0	2	2002	2	6	0	0	13249	9571	6922	3215	3	49	19556	3133	3811	15	43	46	28162	15562	12461	13882	2000	2000	28586	28453	28655	28579	28561
64004	28615	221	0	5	0	6	0	0	2	12	1	0	0	0	4778	28519	2	2	17408	4000	2000	2000	2000	2000	21801	16000	14	0	0	21855	28405	28636	3	10	4000	2000	2000	4000	4000	28515	28592	1	1	61001	1000	1000	0	2000	0	0	0	2000	45	0	2	2002	2	6	4	0	13358	9410	6987	3248	3	46	19696	3226	3805	17	53	50	28139	15324	12472	14045	2000	2000	28373	28529	28634	28520	28592
64004	28557	222	0	7	0	6	0	0	0	0	3	1	0	0	4747	28581	0	0	17285	4000	2000	2000	2000	2000	21811	16000	14	0	0	21851	28475	28651	3	10	4000	2000	2000	4000	4000	28585	28612	1	1	61001	1000	1000	0	2000	0	6	0	2002	40	0	0	2002	2	6	0	0	13164	9717	6942	3243	3	43	19590	3215	3811	16	49	45	28175	15161	12563	13949	2000	2000	28529	28556	28660	28754	28595
64004	28491	222	0	11	0	4	0	0	0	6	1	0	0	0	4863	28464	2	2	17208	4000	2000	2000	2000	2000	21805	16000	14	1	8	21911	28396	28590	3	10	4000	2000	2000	4000	4000	28586	28592	1	1	61001	1000	1000	0	2000	0	0	0	2002	48	0	2	2002	2	6	0	0	13248	9486	6984	3171	2	41	19577	3165	3809	15	39	42	28183	15308	12566	14153	2000	2000	28691	28591	28662	28642	28599
64004	28536	223	0	6	0	3	0	0	0	0	3	1	0	0	4841	28565	2	2	17393	4000	2000	2000	2000	2000	21800	16000	12	1	8	21895	28437	28696	3	10	4000	2000	2000	4000	4000	28433	28653	1	1	61001	1000	1000	0	2000	0	6	0	2002	46	0	2	2002	2	6	0	0	13416	9479	6947	3187	3	43	19636	3187	3805	18	46	47	28194	15026	12390	13936	2000	2000	28540	28663	28648	28534	28538
64004	28625	221	0	8	0	9	0	0	0	0	3	0	0	0	4862	28504	2	2	17483	4000	2000	2000	2000	2000	21803	16000	18	1	0	21863	28332	28679	3	10	4000	2000	2000	4000	4000	28563	28548	1	1	61001	1000	1000	0	2000	0	6	0	2002	48	0	2	2002	2	0	0	0	13247	9378	6979	3228	4	45	19454	3140	3819	20	43	43	28186	15193	12453	13898	2000	2000	28604	28529	28608	28574	28602

Count: 8

Code:

  st1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	23	37	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320206	80084	620	1	1	0	0	0	0	12	6	0	4097	80029	16	0	0	25	326204	100	166026	160000	100	160000	160000	500	3072677	1296890	80024	0	80045	80045	0	3	27	320326	200	160000	160000	200	320000	320000	80045	80049	1	1	80201	100	99	100	100	80000	80000	100	160000	34	0	0	160002	0	0	1855	160062	2	34	0	0	5109	1	17	2	1	80042	160000	160000	100	80046	80050	80046	80046	80050
320204	80049	620	0	0	0	0	0	0	0	3	0	5728	80030	16	16	0	25	326097	100	166563	160060	100	160000	160000	500	2239669	1295473	80024	0	80209	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	34	0	0	160002	0	0	2	160000	2	34	0	0	5125	1	17	1	1	80042	160000	160000	100	80046	80046	80046	80046	80050
320204	80049	620	0	0	0	0	0	0	0	3	0	6078	80030	16	16	0	25	326345	100	165719	160000	100	160000	160000	500	2198332	1294670	80024	0	80045	80049	0	3	27	320326	200	160000	160000	200	320000	320000	80045	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	160002	1	0	2	160002	2	34	0	0	5109	1	17	1	1	80042	160000	160000	100	80046	80046	80050	80046	80045
320204	80045	620	0	0	0	1	4	0	0	3	0	3737	80034	16	16	0	25	326151	100	166403	160000	100	160000	160000	500	2138880	1295872	80024	0	80045	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	34	0	0	160002	0	0	2	160002	2	34	0	0	5109	1	17	1	2	80042	160000	160000	100	80046	80050	80046	80046	80046
320204	80212	620	0	0	0	0	0	0	0	9	0	4513	80029	16	16	89	25	325900	100	164258	160000	100	160000	160000	500	2229303	1302431	80024	0	80045	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80219	80049	1	1	80201	100	99	100	100	80000	80000	100	160000	34	0	0	160002	1	0	2	160002	2	34	0	0	5109	1	17	1	1	80042	160000	160000	100	80046	80046	80046	80046	80050
320204	80048	620	0	0	0	0	0	0	0	3	0	6020	80030	16	16	0	25	325561	100	164272	160000	100	160000	160000	500	2228655	1301098	80024	0	80049	80217	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	34	0	0	160062	1	0	2	160002	2	34	0	0	5109	1	17	1	1	80041	160000	160000	100	80046	80046	80049	80046	80050
320204	80044	620	0	0	0	0	0	0	0	3	0	6067	80030	16	16	0	25	323777	100	162052	160000	100	160000	160000	500	2079451	1302119	80025	0	80045	80045	0	16	2796	324848	200	160000	160000	200	320000	320000	80049	80048	1	1	80201	100	99	100	100	80000	80000	100	160000	34	0	0	160002	0	0	2	160060	0	34	0	0	5109	1	17	1	1	80042	160000	160000	100	80046	80046	80049	80046	80050
320204	80049	643	0	0	0	0	0	0	9	0	0	5597	80030	16	16	0	25	326147	100	165089	160000	100	160000	160000	500	2138880	1298525	80025	0	80048	80045	0	3	123	320100	200	160000	160000	200	320000	320000	80045	80048	1	1	80201	100	99	100	100	80000	80000	100	160000	34	0	0	160002	1	0	2	160002	2	34	0	0	5109	1	17	1	1	80043	160000	160000	100	80046	80050	80046	80046	80046
320204	80045	621	0	0	0	0	0	0	0	6	0	4486	80033	16	16	0	25	324563	100	168467	160000	100	160000	160000	500	1919834	1298510	80024	0	80045	80045	0	3	124	320100	200	160120	160000	200	320000	320000	80049	80048	1	1	80201	100	99	100	100	80000	80000	100	160000	34	0	0	160000	1	0	2	160002	2	34	0	0	5109	1	17	2	1	80046	160000	160000	100	80213	80046	80046	80046	80050
320204	80050	621	0	0	0	0	0	0	0	3	0	7025	80030	16	16	0	25	325543	100	164833	160000	100	160118	160000	500	2233434	1311376	80023	3	80211	80044	0	3	27	320100	200	160000	160000	200	320000	320000	80214	80045	2	1	80201	100	99	100	100	80000	80000	100	160000	34	0	0	160002	1	0	2	160002	2	34	0	0	5109	1	17	1	1	80044	160000	160000	100	80045	80046	80045	80046	80050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320026	80058	643	0	0	0	0	0	12	3	3281	1	80030	16	16	0	25	326546	10	164335	160000	10	160000	160000	50	2156842	1302274	0	80024	80045	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	380	160002	2	42	0	0	5021	4	17	3	5	80042	160000	160000	10	80046	80046	80046	80046	80046
320024	80046	621	0	0	0	0	0	0	3	4499	1	80030	16	16	0	25	325473	10	167055	160000	10	160000	160000	50	2158244	1303862	1	80024	80045	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	2	0	422	160000	2	42	0	0	5021	3	17	4	5	80042	160000	160000	10	80046	80046	80047	80046	80046
320024	80045	620	0	0	0	0	0	0	0	4602	1	80030	16	16	0	25	324316	10	166574	160000	10	160000	160000	50	2156312	1290543	0	80023	80045	80045	0	3	27	320236	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	5	160002	2	42	0	0	5021	4	17	4	5	80044	160000	160000	10	80046	80046	80046	80046	80046
320024	80047	626	0	0	0	0	0	0	0	4470	1	80030	16	16	0	25	324872	10	166078	160000	10	160000	160000	50	2142761	1298834	0	80024	80045	80045	0	7	27	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	2	160002	1	0	5	160002	2	42	0	0	5021	5	17	5	4	80042	160000	160000	10	80046	80046	80046	80046	80045
320024	80045	620	0	0	0	0	0	9	3	6648	1	80030	16	16	0	25	323707	10	166918	160000	10	160000	160000	50	2229502	1302434	0	80024	80045	80045	0	3	26	320010	20	160000	160000	20	320000	320000	80045	80213	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	282	160002	2	42	0	0	5021	4	17	3	5	80042	160000	160000	10	80046	80045	80045	80046	80045
320024	80045	621	0	0	0	0	0	9	3	3462	1	80031	16	16	0	25	325240	10	164796	160000	10	160000	160108	50	2235163	1298338	0	80024	80045	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	0	5021	5	17	4	5	80042	160000	160000	10	80046	80047	80046	80046	80046
320024	80045	620	1	0	0	0	0	0	3	3468	1	80030	16	16	0	25	325661	10	166544	161740	10	163068	160108	50	2236174	1305621	0	80024	80045	80045	85	3	27	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	2	160002	2	48	0	0	5035	5	17	4	5	80042	160000	160000	10	80046	80046	80046	80045	80046
320024	80044	620	0	0	0	0	0	0	3	7481	1	80029	16	16	0	25	324506	10	163719	160000	10	160000	160000	50	2144990	1297026	0	80024	80045	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	221	160002	2	42	0	0	5021	5	17	3	5	80042	160000	160000	10	80046	80046	80046	80046	80046
320024	80044	621	0	0	0	0	0	12	3	4996	1	80196	16	16	0	25	325639	10	163527	160000	10	160000	160108	50	2158997	1302543	0	80024	80045	80045	84	3	27	320010	20	160000	160000	20	320000	320000	80047	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	1	0	185	160002	2	42	0	0	5035	3	17	4	5	80042	160000	160000	10	80045	80046	80046	80046	80046
320024	80045	621	0	0	0	0	0	0	4	6085	1	80030	16	16	0	25	325829	10	164155	160000	10	160000	160000	50	2238442	1296060	0	80024	80045	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	0	5021	5	17	5	5	80042	160000	160000	10	80046	80046	80046	80046	80046

ST1 (multiple, 4 regs, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations