Firestorm: ST1 (multiple, 4 regs, 4S) measurements

Code:

  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	24	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
64005	29386	238	2	10	0	9	0	0	0	0	1	0	4663	29162	4	4	23448	4000	4000	4000	21609	2	17009	0	28740	29377	3	10	4000	4000	8000	29302	29275	1	1	61001	1000	1000	0	4000	0	0	0	4000	0	0	0	4000	12	0	0	13241	9398	6920	3138	4	38	20449	3346	3809	11	44	41	28699	16328	13105	14971	4000	29486	29492	29539	29881	29597
64004	29479	238	0	8	0	9	0	0	0	0	1	0	4640	29305	4	0	23283	4000	4000	4000	21601	5	17052	0	28749	29633	3	10	4000	4000	8000	29243	29446	1	1	61001	1000	1000	0	4000	0	12	0	4000	0	0	0	4000	12	0	0	13368	9511	7010	3147	5	41	20420	3294	3821	13	41	39	28757	16105	13113	15083	4000	29552	29655	29565	29422	29568
64004	29600	237	0	8	0	6	0	0	0	0	1	0	4646	29243	0	0	23377	4000	4000	4004	21592	1	17072	0	28635	29511	3	10	4000	4000	8000	29386	29505	1	1	61001	1000	1000	0	4000	0	0	0	4000	0	0	0	4000	8	0	0	13211	9551	6965	3180	5	41	20411	3346	3822	11	44	37	28715	16192	13292	14613	4000	29509	29559	29485	29486	29493
64004	29496	236	0	10	1	8	0	0	0	18	1	0	4591	29408	0	0	23098	4000	4000	4000	21609	4	17056	0	28727	29333	3	10	4000	4000	8000	29234	29326	1	1	61001	1000	1000	0	4000	0	8	0	4000	1	0	0	4000	0	0	0	13115	9368	6945	3177	6	44	20385	3384	3818	12	42	42	28664	16214	13231	14840	4000	29378	29359	29764	30196	29410
64004	29423	236	0	6	0	6	0	0	0	0	1	0	4687	29167	0	0	23233	4000	4000	4000	21618	4	17029	0	28644	29403	3	10	4000	4000	8000	29206	29237	1	1	61001	1000	1000	0	4000	0	0	0	4000	0	0	0	4000	8	2	0	13107	9487	7006	3194	2	42	20383	3321	3814	10	41	36	28660	16198	12909	14813	4000	29365	29462	29506	29365	29437
64004	29349	236	0	10	0	14	0	1	0	0	1	0	4665	29262	0	0	23274	4000	4000	4000	21618	3	17044	0	28704	29414	3	10	4000	4000	8008	29348	29280	1	1	61001	1000	1000	0	4000	0	8	0	4000	0	0	0	4000	8	0	0	13256	9647	6953	3097	6	37	20485	3288	3814	11	34	43	28625	15962	13117	14617	4000	29295	29470	29375	29458	29359
64004	29482	237	0	6	0	7	0	0	0	0	1	0	4724	29140	0	0	23248	4000	4000	4000	21605	0	17037	0	28629	29369	3	10	4000	4000	8000	29320	29263	1	1	61001	1000	1000	0	4000	0	8	0	4000	0	0	0	4000	0	0	0	13153	9598	6921	3162	3	39	20535	3268	3819	7	39	39	28618	16033	13250	14686	4000	29457	29418	29361	29426	29433
64004	29307	236	0	11	0	6	0	0	0	0	1	0	4746	29170	0	0	23384	4000	4000	4000	21607	2	17058	0	28561	29513	9	10	4000	4000	8000	29329	29350	1	1	61001	1000	1000	0	4000	0	8	2	4000	0	0	380	4000	8	0	0	13381	9417	6949	3172	3	40	20508	3363	3818	17	41	39	28729	16183	13067	15036	4000	29470	29450	29379	29445	29450
64004	29512	237	0	9	0	9	0	0	0	0	1	0	4634	29226	0	0	23390	4000	4000	4000	21609	2	17051	0	28679	29417	3	10	4000	4000	8008	29271	29356	1	1	61001	1000	1000	0	4000	0	0	0	4000	0	0	3	4000	8	0	0	13115	9558	6958	3163	5	38	20449	3337	3813	12	40	43	28750	16021	12994	14655	4000	29456	29422	29444	29296	29491
64004	29444	236	0	11	0	8	0	0	0	9	1	1	4760	29284	0	0	23339	4000	4000	4000	21603	0	17053	0	28689	29450	3	10	4000	4000	8000	29355	29323	1	1	61001	1000	1000	0	4000	0	0	0	4000	0	0	0	4000	0	0	0	13296	9522	6933	3176	6	38	20533	3331	3817	13	45	41	28784	16107	13311	14792	4000	29440	29555	29452	29544	29474

Count: 8

Code:

  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	160042	1241	0	0	3	0	0	12	0	1	0	0	0	160027	16	16	0	25	320100	100	320240	100	320000	500	7359352	160566	160042	160042	79978	3	80024	320100	200	320000	200	640000	160040	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320000	90	0	6	320002	2	34	0	0	5110	1	17	1	1	160047	320000	100	160050	160051	160051	160050	160043
320204	160042	1240	0	0	0	0	0	0	0	1	0	0	0	160025	16	16	0	25	320100	100	320000	100	320000	500	7359424	160017	160042	160042	79980	3	80024	320100	200	320000	200	640000	160042	160050	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320000	98	0	2	320002	2	34	0	0	5110	1	17	1	1	160039	320000	100	160043	160051	160043	160041	160041
320204	160042	1241	0	0	0	0	0	0	9	0	0	0	0	160027	16	16	0	25	320100	100	320000	100	320000	500	7359424	160134	160042	160040	79980	3	80122	320100	200	320000	200	640000	160042	160179	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	106	2	2	320002	2	34	0	0	5110	1	17	1	1	160048	320000	100	160051	160180	160050	160051	160043
320204	160042	1242	0	0	0	0	0	12	3	1	0	0	0	160027	16	16	0	25	320100	100	320000	100	320000	500	7359424	160026	160042	160042	79978	15	80024	320100	200	320000	200	640000	160179	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	144	0	2	320000	0	34	0	0	5110	1	17	1	1	160037	320000	100	160043	160041	160041	160041	160043
320204	160042	1241	0	0	0	0	0	0	3	0	0	1	0	160025	0	0	0	25	320100	100	320000	100	320000	500	7359352	160026	160042	160050	79980	3	80022	320100	200	320000	200	640240	160042	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320002	97	0	3	320002	2	34	0	0	5110	1	17	1	1	160039	320000	100	160051	160043	160041	160051	160043
320204	160042	1241	0	0	0	0	0	0	0	0	0	0	0	160036	16	16	0	25	320100	100	320000	100	320000	500	7364188	160015	160042	160042	79980	3	80024	320100	200	320000	200	640000	160042	160049	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	150	0	3	320002	0	34	0	0	5128	1	17	1	1	160039	320000	100	160041	160043	160043	160043	160043
320204	160040	1241	0	0	0	1	0	6	0	0	0	0	0	160027	16	16	0	25	320100	100	320000	100	320000	500	7359424	160017	160042	160040	80056	3	80024	320100	200	320000	200	640000	160042	160050	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	100	0	2	320062	2	0	0	0	5110	1	17	1	1	160037	320000	100	160041	160041	160041	160043	160051
320204	160042	1240	0	0	0	0	0	12	0	0	0	0	0	160025	16	0	2	25	320100	100	320000	100	320000	500	7359424	160017	160187	160042	79980	3	80022	320100	200	320000	200	640000	160040	160042	1	1	80201	100	99	100	100	80000	80000	100	320062	0	34	0	0	320002	64	0	797	320002	0	0	0	0	5110	1	17	1	1	160039	320000	100	160043	160043	160041	160181	160062
320204	160042	1241	0	0	0	1	2	264	3	0	0	0	0	160303	16	16	295	145	320340	100	320240	100	320216	511	7374244	160490	160672	160597	80142	51	80330	320316	200	320240	200	640720	160745	160318	4	1	80201	100	99	100	100	80000	80000	100	320240	0	34	58	0	320242	2	4	3196	320242	2	34	0	0	5110	1	17	1	1	160046	320000	100	160043	160043	160043	160043	160058
320204	160050	1241	0	0	0	0	0	0	3	0	0	1	0	160027	16	16	4	25	320100	100	320000	100	320000	500	7359424	160017	160042	160042	79978	3	80024	320100	200	320000	200	640000	160040	160040	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320000	96	0	2	320000	2	0	0	0	5110	1	17	1	1	160037	320000	100	160041	160043	160043	160043	160044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	160042	1241	0	0	0	0	0	0	0	0	3	0	0	0	160027	16	16	0	25	320010	10	320000	10	320000	50	7359424	160026	0	160042	160051	79989	3	80032	320010	20	320000	20	640000	160042	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	320002	0	0	278	320004	2	34	0	0	0	5020	13	17	5	13	160048	0	320000	10	160052	160051	160051	160058	160043
320024	160042	1240	0	0	1	0	0	0	0	0	3	0	0	0	160035	0	16	0	25	320010	10	320000	10	320000	50	7359856	160017	0	160051	160042	79980	3	80024	320010	20	320000	20	640000	160042	160113	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	320000	0	0	380	320002	2	34	0	0	0	5020	13	17	14	5	160039	0	320000	10	160043	160043	160043	160043	160043
320024	160042	1245	0	0	0	0	0	0	0	438	267	1	0	0	160025	16	16	0	25	320010	10	320000	10	320000	50	7359856	160017	0	160042	160042	79980	3	80032	320010	20	320000	20	640000	160042	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	0	320002	0	0	407	320002	2	34	0	0	0	5020	5	17	14	5	160039	0	320000	10	160043	160043	160043	160043	160051
320024	160042	1240	0	0	0	0	0	0	0	0	3	0	0	0	160035	16	16	0	25	320010	10	320000	10	320000	50	7359784	160017	0	160041	160042	79980	3	80033	320010	20	320000	20	640000	160042	160050	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	320002	3	0	468	320002	2	34	0	0	0	5020	13	17	14	13	160046	0	320000	10	160050	160052	160051	160050	160043
320024	160062	1240	0	0	0	0	0	0	0	0	3	0	0	0	160027	16	16	0	25	320010	10	320060	10	320000	50	7359424	160017	0	160051	160180	79980	3	80024	320010	20	320000	20	640000	160042	160040	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	320002	0	0	434	320002	2	34	0	0	0	5020	6	17	13	13	160039	0	320000	10	160043	160043	160181	160043	160051
320024	160045	1240	0	0	0	0	0	0	0	4884	4667	0	0	0	160027	16	16	0	25	320070	10	320000	10	320000	50	7359928	160017	0	160048	160042	79980	3	80022	320118	20	320000	20	640000	160051	160042	2	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	320002	0	0	257	320002	2	34	0	0	0	5020	13	17	6	14	160037	0	320000	10	160181	160043	160043	160043	160043
320024	160180	1241	0	0	0	0	0	0	0	0	3	0	0	0	160027	16	16	2	25	320010	10	320000	10	320000	50	7364572	160017	0	160049	160042	79978	3	80022	320010	20	320000	20	640000	160042	160050	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	29	320000	0	0	440	320002	2	34	0	0	0	5020	14	26	5	11	160039	0	320000	10	160043	160043	160041	160043	160043
320024	160043	1245	0	0	1	0	0	1	0	72	3	0	0	0	160027	16	16	0	25	320070	10	320000	10	320000	50	7359352	160017	0	160120	160042	79980	3	80022	320010	20	320000	20	640000	160050	160042	2	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	320002	0	2	368	320002	2	34	0	0	0	5032	10	17	15	10	160048	0	320000	10	160052	160051	160052	160041	160043
320024	160042	1240	0	0	0	0	0	0	0	36	3	0	0	0	160027	16	16	223	115	320250	10	320240	10	320216	50	7378696	164042	0	160315	160456	80212	15	80123	320226	20	320240	20	640480	160326	160456	3	1	80021	10	9	10	10	80000	80000	10	320300	4	38	1086	320062	1	0	2693	320122	2	34	0	0	0	5055	7	44	15	5	160397	0	320000	10	160041	160043	160043	160043	160041
320024	160077	1240	0	0	0	0	0	0	0	0	0	0	0	0	160027	0	16	0	25	320010	10	320000	10	320000	50	7359784	160017	0	160042	160040	79980	3	80033	320010	20	320000	20	640000	160042	160040	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	320002	0	0	380	320002	2	0	0	0	0	5020	13	17	15	14	160039	0	320000	10	160043	160043	160043	160043	160052

ST1 (multiple, 4 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations