Firestorm: ST1 (multiple, 4 regs, 8B) measurements

Code:

  st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64006	28686	223	4	1	2	0	0	1	1	0	0	0	3	0	0	4774	28501	2	2	17483	4004	2000	2000	2000	2000	21811	16000	16	21945	28418	28660	9	10	4000	2000	2000	4000	4000	28654	28665	2	1	61001	1000	1000	2003	2	6	1	2002	2	2	2	2000	2	6	2	1	13253	9551	6963	3206	0	40	19634	3287	3808	10	41	53	28131	15111	12624	14120	2000	2000	28539	28741	28589	28583	28644
64004	28669	223	0	1	0	1	1	1	1	0	0	0	3	0	0	4832	28491	2	2	17501	4000	2000	2000	2000	2000	21812	16000	15	21906	28473	28561	3	10	4000	2000	2000	4000	4000	28572	28657	1	1	61001	1000	1000	2003	3	6	1	2002	1	0	2	2000	2	6	2	1	13302	9504	6891	3120	0	39	19728	3243	3801	16	46	39	28129	15404	12522	14165	2000	2000	28705	28608	28736	28718	28565
64004	28736	222	0	1	1	1	0	0	1	0	0	0	3	0	0	4934	28527	0	0	17392	4000	2000	2000	2000	2000	21823	16000	11	21906	28439	28537	3	10	4000	2000	2000	4000	4000	28584	28613	1	1	61001	1000	1000	2003	4	6	0	2002	1	0	11	2000	0	0	2	0	13641	9839	7049	3239	1	39	19551	3225	3807	8	42	40	28309	14950	12642	13583	2000	2000	28737	28673	28727	28734	28655
64004	28490	221	0	1	0	0	0	0	0	0	0	0	3	1	0	4873	28448	0	0	17424	4000	2000	2000	2000	2000	21814	16000	6	21903	28398	28623	3	10	4000	2000	2000	4000	4000	28436	28679	1	1	61001	1000	1000	2003	2	4	0	2002	0	2	2	2000	2	6	2	0	13085	9429	6968	3195	0	42	19636	3138	3804	12	45	45	28188	15143	12507	13632	2000	2000	28533	28695	28665	28544	28533
64004	28673	221	0	1	1	0	0	1	1	0	0	0	3	0	0	4744	28561	0	2	17462	4000	2000	2000	2000	2000	21810	16000	18	21916	28435	28593	3	10	4000	2000	2000	4000	4000	28598	28505	1	1	61001	1000	1000	2002	3	6	0	2002	0	1	5	2000	2	6	2	0	13418	9678	6983	3249	1	44	19777	3228	3800	16	42	44	28091	15574	12500	14070	2000	2000	28675	28663	28658	28565	28643
64004	28646	220	0	1	1	1	1	1	1	0	0	0	3	0	0	4788	28557	2	2	17593	4000	2000	2000	2000	2000	21812	16000	15	21873	28402	28669	3	10	4000	2000	2000	4000	4000	28435	28617	1	1	61001	1000	1000	2002	4	6	1	2002	0	2	2	2000	2	6	2	1	13413	9745	7001	3147	1	45	19550	3186	3801	12	41	40	28111	15304	12518	14094	2000	2000	28607	28556	28584	28522	28654
64004	28565	221	0	1	0	1	1	1	0	0	0	0	3	0	0	4846	28407	2	2	17407	4000	2000	2000	2000	2000	21809	16000	16	21923	28244	28566	3	10	4000	2000	2000	4000	4000	28535	28693	1	1	61001	1000	1000	2002	3	6	1	2002	2	2	2	2000	2	6	2	1	13157	9716	6977	3254	0	33	19704	3255	3804	15	45	47	28229	15364	12497	14088	2000	2000	28507	28586	28520	28512	28576
64004	28619	222	0	1	1	1	1	1	1	0	0	0	3	0	0	4715	28483	2	2	17427	4000	2000	2000	2000	2000	21804	16000	16	21883	28397	28633	3	10	4000	2000	2000	4000	4000	28531	28473	1	1	61001	1000	1000	2003	3	6	1	2002	12	1	2	2000	2	6	2	1	13195	9752	6992	3234	0	54	19609	3227	3800	13	42	51	28144	15287	12370	13921	2000	2000	28592	28580	28723	28412	28542
64004	28620	222	0	1	1	1	1	0	1	0	0	0	3	0	0	4872	28505	2	2	17436	4000	2000	2000	2000	2000	21809	16000	17	21910	28446	28503	3	10	4000	2000	2000	4000	4000	28681	28497	1	1	61001	1000	1000	2003	3	6	1	2002	0	0	5	2000	2	6	2	1	13441	9477	6971	3206	0	44	19633	3204	3807	18	41	40	28206	15095	12409	13887	2000	2000	28552	28576	28613	28723	28521
64004	28622	223	0	1	1	2	1	1	1	0	0	0	3	0	0	4788	28560	2	2	17337	4000	2000	2000	2000	2000	21811	16000	11	21866	28256	28751	3	10	4000	2000	2000	4000	4000	28726	28532	1	1	61001	1000	1000	2002	2	6	1	2002	0	0	2	2000	2	6	2	1	13169	9730	6970	3173	2	44	19551	3151	3805	11	46	44	28199	15084	12482	13691	2000	2000	28625	28553	28631	28732	28538

Count: 8

Code:

  st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320206	80071	621	1	0	1	0	0	0	0	14	0	7439	0	80038	16	0	0	25	325616	100	166858	160000	100	160000	160000	500	2158817	1294614	0	80025	80048	80047	0	3	41	320100	200	160000	160000	200	320000	320000	80050	80058	1	1	80201	100	99	100	100	80000	80000	100	160014	0	34	0	1	160002	0	0	20	160002	0	0	0	0	0	0	0	5109	0	1	17	1	1	80042	0	160000	160000	100	80046	80046	80053	80046	80046
320204	80045	621	0	0	0	0	0	0	6	3	0	6118	0	80033	16	16	0	25	325247	100	165883	160000	100	160000	160000	500	2158849	1299726	0	80024	80047	80046	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160014	14	36	0	0	160016	1	0	18	160002	2	34	0	0	0	0	0	5109	0	1	17	1	1	80045	0	160000	160000	100	80046	80049	80045	80046	80046
320204	80046	620	0	0	0	0	0	0	0	3	1	5004	0	80522	0	0	0	25	327564	100	165258	160000	100	160118	160216	500	2231087	1294828	0	80024	80052	80052	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80046	1	1	80201	100	99	100	100	80000	80000	100	160014	0	34	0	0	160002	0	0	17	160002	2	34	0	0	0	0	0	5109	0	1	17	1	1	80041	0	160000	160000	100	80046	80046	80049	80046	80051
320204	80045	620	0	0	0	0	0	0	21	14	0	5443	1	80030	0	16	0	25	325645	100	164907	160000	100	160000	160000	500	3679175	1295403	0	80033	80045	80046	0	3	32	320100	200	160000	160000	200	320000	320000	80050	80050	1	1	80201	100	99	100	100	80000	80000	100	160015	15	0	0	0	160014	1	0	17	160002	2	34	0	0	0	0	0	5109	0	1	17	1	1	80042	0	160000	160000	100	80046	80046	80045	80046	80046
320204	80045	620	0	0	0	0	0	0	0	0	0	5296	0	80044	16	16	0	25	325971	100	165724	160000	100	160000	160000	500	2233992	1296651	0	80026	80050	80051	0	3	32	320100	200	160000	160000	200	320000	320000	80059	80058	1	1	80201	100	99	100	100	80000	80000	100	160016	15	38	0	0	160016	0	0	14	160002	14	34	0	0	0	0	0	5109	0	1	17	1	1	80048	0	160000	160000	100	80046	80046	80050	80046	80045
320204	80045	620	0	0	0	0	0	0	12	3	0	5169	0	80030	16	16	0	25	325009	100	163870	160000	100	160000	160000	500	2078862	1299158	0	80024	80045	80045	0	3	31	320100	200	160000	160000	200	320000	320000	80052	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	0	160002	0	1	2	160002	2	34	0	0	0	0	0	5109	0	1	17	1	1	80042	0	160000	160000	100	80046	80046	80046	80046	80046
320204	80045	620	0	0	0	0	0	0	0	6	0	5260	0	80030	16	0	0	25	325077	100	166597	160000	100	160000	160000	500	2236086	1295500	0	80023	80045	80045	0	3	30	320100	200	160000	160000	200	320000	320000	80048	80049	1	1	80201	100	99	100	100	80000	80000	100	160014	0	34	0	0	160002	0	0	17	160002	0	34	0	0	0	0	0	5109	0	1	17	1	1	80050	0	160000	160000	100	80046	80046	80046	80046	80049
320204	80048	620	0	0	0	0	0	0	0	3	0	2611	0	80033	16	16	1	25	325142	100	164489	160000	100	160000	160000	500	2399920	1300699	0	80026	80049	80048	0	3	33	320100	200	160000	160000	200	320000	320000	80050	80050	1	1	80201	100	99	100	100	80000	80000	100	160014	15	0	0	0	160016	0	2	20	160002	16	0	0	0	0	0	0	5109	0	1	17	1	1	80047	0	160000	160000	100	80046	80045	80046	80045	80046
320204	80045	620	0	0	0	0	0	0	0	3	0	5566	0	80030	0	16	0	25	326096	100	166738	160000	100	160000	160000	500	2397980	1300837	0	80024	80045	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160014	14	36	0	2	160014	0	1	16	160000	14	34	0	0	0	0	0	5109	0	1	17	1	1	80047	0	160000	160000	100	80060	80061	80051	80051	80046
320204	80058	620	1	0	0	0	0	0	0	3	0	5181	0	80030	16	16	0	25	325332	100	164449	160000	100	160000	160000	500	2151817	1294800	0	80024	80044	80045	0	3	34	320100	200	160000	160000	200	320000	320000	80049	80046	1	1	80201	100	99	100	100	80000	80000	100	160000	0	36	0	0	160002	0	0	2	160002	2	34	0	0	0	0	0	5109	0	1	17	1	1	80042	0	160000	160000	100	80046	80046	80050	80046	80046

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320026	80058	621	1	0	0	0	0	0	132	18	0	0	4873	1	80030	16	16	0	25	324705	10	167018	160000	10	160000	160000	50	2479520	1303087	1	0	5	80025	80052	80052	0	3	34	320010	20	160000	160000	20	320240	320000	80051	80045	1	1	80021	10	9	10	10	80000	80000	10	160014	14	44	0	0	160002	0	0	21	160002	16	44	14	0	5019	0	0	19	17	10	19	80217	160000	160000	10	80052	80051	80046	80053	80052
320024	80053	620	1	0	0	1	0	0	12	19	0	0	5430	1	80037	15	16	0	25	325563	10	164801	160000	10	160000	160108	50	2559748	1306079	0	1	5	80037	80052	80050	84	3	34	320010	20	160000	160000	20	320000	320000	80051	80051	1	1	80021	10	9	10	10	80000	80000	10	160000	14	44	0	0	160016	0	1	2	160002	2	42	14	0	5019	0	0	17	17	18	13	80042	160000	160000	10	80052	80053	80052	80046	80053
320024	80052	620	0	0	0	1	0	1	0	17	0	0	5951	1	80035	16	16	3	25	324931	10	165237	160000	10	160000	160000	50	2399927	1297206	0	0	0	80024	80045	80050	0	3	34	320010	20	160000	160000	20	320000	320000	80062	80063	1	1	80021	10	9	10	10	80000	80000	10	160014	0	44	0	0	160016	1	0	18	160002	16	44	0	0	5019	0	0	19	26	16	19	80049	160000	160000	10	80046	80052	80054	80063	80046
320024	80045	621	1	1	0	1	0	0	0	18	0	0	5781	0	80036	16	16	3	25	325291	10	165493	160000	10	160000	160000	50	2210616	1294563	2	0	5	80024	80045	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80050	1	1	80021	10	9	10	10	80000	80000	10	160016	0	48	0	0	160016	1	0	21	160002	16	44	14	0	5019	0	0	18	17	19	16	80048	160000	160000	10	80052	80046	80221	80051	80052
320024	80051	621	1	0	1	1	0	0	0	14	0	0	4391	0	80030	16	16	0	25	325612	10	165889	160000	10	160000	160108	50	2278705	1293691	4	0	5	80024	80062	80063	0	3	33	320010	20	160000	160000	20	320000	320000	80052	80045	1	1	80021	10	9	10	10	80000	80000	10	160014	14	44	0	1	160002	0	1	16	160002	16	44	14	0	5019	0	0	17	17	10	18	80047	160000	160000	10	80052	80053	80046	80052	80221
320024	80052	620	1	0	1	1	0	0	0	19	0	0	4090	1	80037	16	15	0	25	325249	10	165799	160000	10	160000	160000	50	3679478	1294059	3	0	5	80037	80052	80052	0	3	44	320236	20	160000	160000	20	320000	320000	80051	80051	1	1	80021	10	9	10	10	80000	80000	10	160000	14	44	0	0	160016	1	0	2	160002	2	42	14	0	5019	5	0	17	17	18	10	80043	160000	160000	10	80052	80052	80053	80045	80053
320024	80051	622	0	0	0	1	0	0	9	17	0	0	4682	1	80038	16	16	0	25	323630	10	162596	160000	10	160000	160000	50	2479776	1317621	2	0	0	80025	80044	80052	0	3	34	320010	20	160000	160000	20	320000	320000	80063	80062	1	1	80021	10	9	10	10	80000	80000	10	160014	0	44	0	1	160076	1	0	27	160002	16	44	0	1	5019	0	0	18	17	18	10	80049	160000	160000	10	80046	80052	80053	80064	80046
320024	80046	620	1	1	1	1	0	0	0	19	0	1	4237	0	80045	16	16	3	25	324550	10	164677	160000	10	160000	160000	50	2211812	1297847	2	0	0	80024	80045	80045	0	3	28	320010	20	160000	160000	20	320000	320000	80045	80051	1	1	80021	10	9	10	10	80000	80000	10	160014	0	42	0	0	160016	0	2	19	160002	16	44	0	0	5019	0	0	12	17	14	18	80049	160000	160000	10	80046	80046	80053	80063	80046
320024	80045	620	1	0	2	0	0	0	12	4	0	0	6941	0	80030	16	16	88	25	324032	10	164616	160000	10	160000	160000	50	2158198	1297289	3	0	5	80027	80051	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160015	16	42	3	0	160002	0	0	16	160002	0	42	0	0	5019	0	0	12	17	17	17	80043	160000	160000	10	80045	80046	80046	80046	80048
320024	80045	621	0	0	0	0	0	0	6	0	0	1	1294	0	80029	0	16	0	25	324923	10	166221	160000	10	160000	160000	50	2223932	1304369	3	0	0	80024	80211	80045	0	7	26	320010	20	160000	160120	20	320000	320000	80378	80045	2	1	80021	10	9	10	10	80000	80000	10	160060	0	42	124	0	160060	0	0	925	160184	2	42	0	0	5062	0	0	19	35	18	18	80197	160000	160000	10	80054	80215	80211	80046	80215

ST1 (multiple, 4 regs, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations