Firestorm: ST1 (multiple, 4 regs, 8H) measurements

Code:

  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	1f	22	23	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
64005	28512	212	1	8	8	0	3	0	0	5063	28132	4	0	22125	4000	4000	4000	21615	17	17033	27812	28319	3	10	4000	4000	8000	28181	28336	1	1	61001	1000	1000	4000	12	4002	10	0	4002	2	0	13576	10182	7234	3365	3	73	19391	3327	3808	19	68	66	27952	14706	11998	13194	4000	28416	28306	28550	28443	28446
64004	28157	213	0	3	6	0	0	1	0	5229	27995	0	0	21992	4000	4000	4000	21626	11	17045	27897	28238	3	10	4000	4000	8000	28038	28169	1	1	61001	1000	1000	4000	8	4000	43	0	4000	0	8	14175	10189	7270	3402	3	66	19357	3346	3814	25	66	67	27985	14499	12023	12648	4000	28372	28245	28132	28401	28481
64004	28214	210	0	3	2	0	0	0	0	5018	28085	0	0	22173	4000	4000	4000	21634	10	17056	27966	28183	3	10	4000	4000	8000	28251	28342	1	1	61001	1000	1000	4000	8	4000	42	0	4000	0	8	13999	10363	7267	3490	1	67	19153	3246	3809	19	65	65	27842	14151	12098	13409	4000	28076	28391	28179	28172	28518
64004	28239	213	0	5	6	0	4	0	0	5150	28102	0	0	22037	4000	4000	4000	21609	10	17046	27906	28054	3	10	4000	4000	8000	28153	28374	1	1	61001	1000	1000	4000	0	4000	44	0	4000	0	8	13939	10281	7224	3527	0	66	19078	3332	3809	11	63	69	27997	14223	11965	12770	4000	28315	28075	28265	28344	28429
64004	28445	217	0	8	4	0	1	1	0	5006	28256	4	4	22130	4000	4000	4000	21614	17	17029	27954	28251	3	10	4000	4000	8000	28135	28181	1	1	61001	1000	1000	4000	8	4000	45	0	4000	0	0	13827	10045	7274	3453	2	67	19235	3317	3809	14	68	63	27906	14720	11762	13209	4000	28314	28205	28332	28317	28376
64004	28440	211	0	7	6	0	1	0	0	5231	28155	0	0	22172	4000	4000	4000	21617	14	17067	27863	28339	3	10	4000	4000	8000	28357	28346	1	1	61001	1000	1000	4000	0	4000	7	3	4000	0	0	14036	10359	7184	3362	3	68	19301	3273	3809	20	67	65	27907	14219	11972	12963	4000	28413	28207	28360	28338	28416
64004	28161	212	0	3	5	0	0	0	0	5267	28103	0	0	22194	4000	4000	4000	21630	11	17046	27975	28164	3	10	4000	4000	8000	28096	28323	1	1	61001	1000	1000	4000	8	4002	43	0	4000	0	8	13919	10072	7097	3395	4	64	19242	3303	3810	11	68	62	28001	14355	12101	13466	4000	28433	28264	28157	28199	28463
64004	28381	211	0	6	5	0	1	0	0	4941	28004	0	0	22148	4000	4000	4000	21630	11	17049	27799	28190	3	10	4000	4000	8000	28210	28004	1	1	61001	1000	1000	4000	0	4000	46	0	4000	0	8	13995	10323	7218	3484	1	60	19103	3411	3812	20	68	63	27894	14465	12010	13372	4000	28278	28203	28220	28305	28392
64004	28377	212	0	2	6	0	0	0	0	5323	28131	0	0	22128	4000	4000	4000	21629	12	17045	27789	28065	3	10	4000	4000	8000	28299	28079	1	1	61001	1000	1000	4000	8	4000	83	6	4000	0	8	13978	10164	7246	3431	3	62	19295	3375	3812	13	61	69	27904	14147	11814	12819	4000	28248	28179	28341	28258	28461
64004	28464	212	0	8	8	0	0	0	0	5024	28053	0	0	22290	4000	4000	4000	21632	10	17048	27994	28279	3	10	4000	4000	8000	28198	28389	1	1	61001	1000	1000	4000	8	4000	47	0	4000	0	8	13825	9777	7189	3408	2	70	19258	3283	3817	14	68	67	27889	15202	12442	14229	4000	28972	28968	28894	29083	28867

Count: 8

Code:

  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	160058	1240	1	0	0	0	0	0	0	12	18	0	1	160037	16	16	10	25	320100	100	320000	100	320000	500	7359908	1	160106	160463	160058	79999	3	80035	320100	200	320000	200	640000	160052	160058	1	1	80201	100	99	100	100	80000	80000	100	320014	14	36	4	0	320016	0	0	601	320002	14	40	14	1	0	0	5110	0	0	3	17	3	3	160056	320000	100	160053	160190	160060	160059	160057
320204	160058	1242	1	0	0	0	0	0	0	0	18	0	1	160037	0	16	5	25	320100	100	320000	100	320000	500	7365056	0	160027	160059	160053	79990	3	80035	320100	200	320000	200	640000	160052	160051	1	1	80201	100	99	100	100	80000	80000	100	320014	14	34	29	0	320016	0	0	18	320002	16	36	14	0	0	0	5110	0	2	2	17	2	2	160055	320000	100	160048	160060	160059	160060	160053
320204	160059	1240	1	0	1	0	1	0	0	66	19	0	1	160032	16	16	5	55	320160	100	320000	100	320000	500	7360246	0	160145	160059	160052	79990	3	80140	320100	200	320000	200	640000	160197	160051	1	1	80201	100	99	100	100	80000	80000	100	320015	14	36	0	2	320076	0	3	14	320002	16	36	14	0	0	0	5110	0	4	2	17	3	3	160049	320000	100	160051	160051	160338	160050	160059
320204	160052	1241	1	0	1	0	0	2	3	396	283	0	1	160311	16	16	226	56	320220	100	320120	100	320216	500	7374635	0	160264	160333	160469	80220	27	80232	320532	200	320360	200	640960	160561	160333	4	1	80201	100	99	100	100	80000	80000	100	320202	14	36	0	0	320016	0	0	18	320002	16	36	14	0	0	0	5110	0	0	1	17	2	2	160054	320000	100	160061	160051	160053	160053	160053
320204	160060	1240	1	0	0	0	1	0	0	0	19	0	1	160043	0	14	9	25	320100	100	320000	100	320000	500	7360268	0	160027	160059	160052	79990	3	80040	320100	200	320140	200	640000	160060	160058	1	1	80201	100	99	100	100	80000	80000	100	320016	15	36	0	0	320016	0	1	17	320002	16	36	14	0	0	0	5110	0	0	3	17	3	3	160058	320000	100	160053	160059	160060	160064	160054
320204	160060	1241	1	0	0	0	1	0	0	0	20	0	1	160037	0	16	2	25	320100	100	320000	100	320000	500	7360268	0	160034	160057	160138	79997	3	80034	320100	200	320000	200	640000	160058	160052	1	1	80201	100	99	100	100	80000	80000	100	320014	15	36	0	0	320016	1	0	20	320002	16	36	14	0	0	0	5110	0	0	1	17	3	2	160055	320000	100	160052	160051	160052	160053	160050
320204	160059	1241	1	0	0	0	0	0	0	0	18	0	1	160032	16	16	9	25	320100	100	320000	100	320000	500	7359932	0	160027	160059	160058	79985	3	80040	320100	200	320000	200	640000	160047	160060	1	1	80201	100	99	100	100	80000	80000	100	320014	14	36	0	1	320016	0	0	18	320002	16	34	14	0	0	0	5110	0	0	1	17	2	2	160044	320000	100	160063	160060	160049	160059	160059
320204	160052	1241	1	0	1	0	1	0	0	0	19	0	1	160045	16	16	2	25	320100	100	320000	100	320000	500	7360244	0	160033	160052	160061	79997	3	80035	320100	200	320000	200	640000	160058	160059	1	1	80201	100	99	100	100	80000	80000	100	320015	15	36	0	1	320016	0	0	22	320002	16	36	14	1	0	0	5110	0	0	2	17	3	3	160055	320000	100	160053	160055	160053	160053	160053
320204	160059	1241	1	0	0	0	0	0	0	0	17	0	1	160033	16	16	4	25	320100	100	320000	100	320000	500	7360244	0	160034	160060	160058	79996	3	80031	320100	200	320000	200	640000	160051	160058	1	1	80201	100	99	100	100	80000	80000	100	320014	14	36	0	0	320016	0	0	19	320002	16	36	14	0	0	0	5110	0	0	1	17	2	2	160055	320000	100	160051	160052	160053	160054	160069
320204	160058	1241	1	0	1	0	0	0	0	12	21	0	1	160044	16	16	5	25	320100	100	320000	100	320000	500	7359836	0	160027	160059	160053	79991	3	80040	320100	200	320000	200	640000	160060	160059	1	1	80201	100	99	100	100	80000	80000	100	320014	14	36	0	0	320016	0	0	20	320002	16	36	14	0	0	0	5110	0	0	2	17	3	2	160056	320000	100	160616	160475	160328	160605	160612

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ld nt uop (e6)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	160042	1240	0	0	0	0	0	0	60	9	0	0	0	160035	16	16	0	25	320010	10	320000	10	320000	50	7359424	0	0	160015	0	160050	160042	79978	3	80034	320010	20	320000	20	640000	160049	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	0	320000	0	0	14	320002	16	0	0	0	5020	0	0	3	17	0	3	3	160039	0	320000	10	160053	160053	160043	160043	160061
320024	160042	1241	1	0	0	0	0	0	24	19	0	0	0	160035	16	16	9	25	320010	10	320000	10	320000	50	7359424	1	0	160017	0	160047	160052	79980	3	80034	320128	20	320000	20	640000	160051	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	0	0	320014	0	0	0	320002	16	34	0	0	5020	0	0	4	17	0	3	2	160039	0	320000	10	160053	160053	160043	160043	160052
320024	160042	1241	0	0	0	0	0	0	9	18	0	0	0	160044	16	16	0	25	320010	10	320000	10	320000	50	7359352	0	0	160017	0	160040	160047	79990	3	80029	320010	20	320000	20	640000	160042	160049	1	1	80021	10	9	10	10	80000	80000	10	320014	0	34	0	0	320016	0	0	2	320002	16	36	0	0	5020	0	0	3	17	0	2	3	160037	0	320000	10	160041	160048	160048	160043	160043
320024	160042	1240	0	1	0	0	0	0	9	20	0	0	0	160027	16	16	0	25	320010	10	320000	10	320000	50	7359856	1	0	160026	0	160454	160049	79989	3	80024	320226	20	320000	20	640000	160042	160040	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	28	0	320000	0	0	5	320000	2	34	0	0	5020	0	0	3	17	0	3	3	160039	0	320000	10	160043	160041	160041	160043	160041
320024	160042	1241	0	0	0	0	0	0	0	3	0	0	0	160027	16	0	0	25	320010	10	320000	10	320000	50	7359352	1	0	160017	0	160042	160040	79980	3	80024	320010	20	320000	20	640000	160050	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	0	320002	0	0	5	320002	2	0	0	0	5020	0	0	2	17	0	3	2	160039	0	320000	10	160043	160043	160043	160043	160052
320024	160622	1248	0	0	1	1	0	1	12	689	0	0	0	160034	16	16	0	25	320010	10	320000	10	320000	50	7359424	1	0	160015	0	160040	160042	79980	3	80022	320010	20	320000	20	640000	160057	160058	1	1	80021	10	9	10	10	80000	80000	10	320000	15	36	0	0	320002	1	1	5	320002	2	34	14	0	5020	0	0	3	17	0	3	3	160157	8	320000	10	160043	160044	160043	160061	160053
320024	160042	1241	1	0	0	0	0	0	1224	1514	0	0	1	160038	16	16	2	25	320010	10	320000	10	320000	50	7360316	0	0	160017	6	160040	160042	79980	3	80029	320010	20	320000	20	640000	160054	160052	1	1	80021	10	9	10	10	80000	80000	10	320014	14	44	0	1	320016	0	1	29	320002	0	42	0	1	5020	0	0	788	17	228	4	3	160051	0	320000	10	160053	160052	160053	160053	160064
320024	160047	1241	1	1	0	0	0	0	0	14	0	0	1	160037	16	16	0	25	320310	10	320000	10	320000	50	7359692	0	0	160038	0	160435	160063	79992	3	84010	320010	20	320360	20	640000	160331	160044	1	1	81863	10	9	10	10	80000	80000	10	320000	0	44	0	0	320002	0	0	0	320002	2	42	0	0	5020	0	0	3	17	0	3	3	160039	0	320000	10	160044	160043	160043	160048	160043
320024	160042	1213	1	0	0	0	0	0	0	17	0	0	0	160025	16	16	0	25	320010	10	320000	10	320000	50	7359448	1	0	160027	0	160042	160040	79980	3	80025	320118	20	320000	20	640000	160040	160047	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	1	18	320002	14	42	0	0	5020	0	0	3	17	0	2	3	160039	0	320000	10	160053	160044	160043	160043	160044
320024	160042	1199	1	0	0	0	0	0	0	14	0	0	1	160025	16	0	0	25	320010	10	320000	10	320000	50	7360028	1	0	160017	0	160052	160043	79980	3	80045	320010	20	320000	20	640000	160040	160043	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	2	320002	0	0	16	320002	16	42	0	0	5020	0	0	3	17	0	3	3	160039	0	320000	10	160053	160048	160041	160043	160055

ST1 (multiple, 4 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations