Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, post-index, 1 reg, 16B)

Test 1: uops

Code:

  st1 { v0.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)18191e1f2223243a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5e5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafl1d cache miss st nonspec (c0)c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
610052939923541000031000455128871102431920001000100010001000500050000515958284082934731020001000300029100291921161001100010001000000100000010003013191935569503211037217373328380283739285221000159801351915035100010002924729297293422927429394
610042935623603010000000466828926002441120001000100010001000500050000515953285022939731020001000300029113291021161001100010001000000100000310003013342955469333105037215673391380494135285461000159171372514985100010002926129371293542907729221
610042931623501000001000459328778112437420001000100010001000500050000715961285592919931020001000300029096292441161001100010001000030100000010002013030948469483074135215833255381583831285591000160071355315199100010002929429352293172943229348
6100429392236020100310004726288810124386200010001000100010005000500006159552863529256310200010003000292532917911610011000100010000001000000100030130019365700831591422162332773809114036285431000161071343614872100010002930729347293882923429227
61004293982360101000000046022884200242312000100010001000100050005000012159512860129199310200010003000291642916511610011000100010000001000000100030130609220692931261402164132723808123532285171000163061364915057100010002935829315293682939129224
610042936123501000001000471628811002436320001000100010001000500050000515945284542924731020001000300029131290951161001100010001000030100010010000013085931769853178135216403299381083331285931000163311360615120100010002945029359294122936729397
6100429264235030000000004807288370024356200010001000100010005000500005159432861729293310200010003000292562924711610011000100010000001001000100030132389335690231411342168832903818114236286061000158731361215079100010002936829420294452923929485
610042936423600010000000470128834002430620001000100010001000500050000515974285742939731020001000300029179291901161002100010001000020100000010002013133930570233137037217643249381393535285871000161221384115105100010002931729373293112942629355
61004293442350200001810004606289010024438200010001000100010005000500001115967285202935431020001000300029263292131161001100010001000000100000010002013232958068903134037217313327382194037285951000162821337015045100010002936029357293842933629371
61004293972360302001200004546288590024319200010001000100010005000500001615964284672937231020001000300029196291321161001100010001000000100000010000013449955069823172134217283287382164335286121000159391366915063100010002930029363293322924829380

Test 2: throughput

Count: 8

Code:

  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f233f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
80205800406440000122080025880251601008010080000801008000041797033758824080015800408004069924369997160100200800002002400008004080090118020110099100100800008000010080000017008000100380000117000511011711800378000080000801008009080092801438009280041
8020480040621000002080025883451601008010080000801008006941797033758824080015800408004069924369997160100200800002022400008004080040118020110099100100800008000010080000017008000140680023117001512611711800378002180000801008004180041800418004180041
8020480040621000002080025880332161229805888000080100800004179703375882408001580040800406992436999716010020080000200240000800768004011802011009910010080000800001008000000008000100680001117000511011711800378000080000801008004180041800418004180041
8020480040621000004080025080251601008010080000801788000041797033759892180054800408004069943369997160100200800002002400008004080040118020110099100100800008000010080000017008000100180001117000511012511800378000080000801008004180041800418004180041
802048004062000000418007488325160100801008000080100800004179703375882408001580040800406992476999716010020080000200240000800408004011802011009910010080000800001008000001700800010038000110000511011711800378000080000801008004180041800418007780041
8020480040643000002080025880251601008010080000801008000041797033758824080015800408004069924369997160100200800952002400008004080040118020110099100100800008000010080000018008000000680000017000511011711800378000080000801008004180041800418004180092
8020480040620000000080025000251601008010080000801008000041797033758824080015800408004069924369997160100200800002002400008004080040118020110099100100800008000010080000017008000010480001117000511011711800378000080000801008004180041800418004180041
8020580040642000004080025080251601748010080000801008000041797033758824080015800408004069955369997160100200800002002400008007780040118020110099100100800008000010080000017908000100680001117000511011711800378000080000801008004180041800418004180041
8020480040620000000080025880251601008010080000801008000041797033759892080015800408004069955370029160100200800002002400008004080076118020110099100100800008000010080000017008000150380000117000511011711800378000080000801008004180041800418004180041
8020480040620000062080025883251601008010080000801008000041797033758824080015800408004069924369997160100200800002002400008004080040118020110099100100800008000010080000017008000100380000117000511011711800378000080000801008004180077800418004180041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f22233a3f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
80025800406200110000200180025891772516001080010800258001080000417862137588240800158009180040699461170071160010208000020240000800408004011800211091010800008000010800087290800011188000112100503881698800378000080000800108004180041800418004180041
80024800406200000016400080025883251600108001080000800108000041786453758824080015800408004069946370020160010208000020240000800408004011800211091010800008000010800007291800070138000102100502081688800378000080000800108004180041800418004180041
800248004062000000004000800250812516001080038800008001080000417864537588240800158004080040699463700201600102080000202400008008980040118002110910108000080000108000792908000800118000112100502061687800378000080000800108004180041800418004180041
800248004062010010018900080025884251600108001080000800108000041786213758824080015800408004069975370020160010208000020240000800408004011800211091010800008000010800087290800080088000012100502081698800378000080000800108004180041800418004180041
800248004062100000012400080025883251600108001080000800108000041786293758824080015800408004069946370020160010208000020240000800408004011800211091010800008000010800077290800081188000182970502071698800378000080000800108004180090800418004180041
80024800406210000000010080025803251600108001080000800108000041786453758824080015800408009169946370020160010208000020240000800408004011800211091010800008000010800008301800080118000112100502081698800378000080000800108004180041800418004180041
8002480040621000000041008002588025160010800108000080010800004178645375882408001580040800406994637005116001020800002024000080040800401180021109101080000800001080007021080008008800011000502081698800378000080000800108004180041800418004180041
8002480040621000000060008002588425160010800108000080010800004178621375882408001580040800406994637002016001020800802024000080040800401180021109101080000800001080007829180007007548000182100502081678800378000080000800108004180041800418004180041
800248004062100000004000800258802516001080039800008001080000417864537588240800158004080040699463700201600102080000202400008004080040118002110910108000080000108000772908000811148000182171502081688800378000080000800108004180041800418004180041
80024800406201000000400180025883251600108001080000800108006941786453758824080015800408004069946370020160010208000020240000800408004011800211091010800008000010800008291800071038000112100502081698800378000080000800108004180041800418004180090