Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, post-index, 1 reg, 1D)

Test 1: uops

Code:

  st1 { v0.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f223a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafl1d cache miss st nonspec (c0)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
6100529689238640000000046522895311245652000100010001000100050005005715960286652960431020001000300029431294681161001010001000100000010001001000300132439375692931420532205733823816185355287941000164191352115062100010002958729562296392961229578
6100429596237040200030046472889300244862000100110021000100150055000615967288782976710102002100130002945729475316100101000100010002331000123851000320132299416697531402552192532673824155552288631001165381386715422100010002974529814297282973729618
6100429454237020200031046452919201248512004100110011002100050005049616020289082973510472002100030032950429796316100101000100010042001002047731001320132599289692531080552193832543825205548286271000166271391915600100010002972829594297142966529582
61004295172390302000151147082887410247702000100010001000100050005000615970289253011631020001000300029477294041161001225710001000100003010001061000200131159295694631791542183634113826185450288211000165211361815206100010002953129486295302951929651
6100429516238020400030046272902300250282000100010001001100050005000115980286412984431020001000300029325294341161001010001000100002010001031000040132659331693731810512294334053832255456287781000162131369615195100010002958829531295272950929502
61004297352390200120210046712926100244892002100010001000100050005000515976287112954391020001000300029408294191161001010001000100402210011016631001203374132029301691031480542193832433823214850290781001163971386815316100010002952129687296272976229407
61004293702380101018182658163504303301221024922201410071007101010005000509171609428931297143615720041005300929588295409161001010001000100143010030034451001300128739188690031332482193332873828135656289581003161061371614941100010002953029659295992955029637
6100429756230021016679252804538292970024460200010001000100010005000500091608329259296507102004100030032952729562116100101000100010020301000104831000020130199500690631410492209732593830225651289181002162811366115137100010002966229552294342946029663
61004294102280211123276176047052910611245402004100210011001100150055000216033285832954672820001000300329331292571161001010001000100000210000231000300131469495695731481522176833253829174946287561000162361364814847100010002946129449294412948729477
610042946223702020001770047142905811243522000100010001000100050005000915954285582937131020001000300029247292731161001010001000100003010001001000200129619243692231121522176233413828135351285011000161521364514920100010002938129423293892940429301

Test 2: throughput

Count: 8

Code:

  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f2223243f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
802058004062100000000410080025880251601008010080000801008000041797033758824080015800408004069924369997160100200800002002400008004080040118020110099100100800008000010080000000800010008000010051101317139800378000080000801008004180041800418004180041
80204800406210000000001008002588025160100801008000080100800004179703375882408001580040800406992436999716010020080000200240000800408004011802011009910010080000800001008000000080000003800010210511012171312800378000080000801008004180041800418004180041
802048004062100000000401080025883251601008010080000801008000041797033758824080015800408004069924369997160100200800002002400008004080040118020110099100100800008000010080000021080001001800011210511010171213800378000080000801008004180041800418004180041
80204800406200000000040108002588325160100801008000080100800004179703375882408001580040800406992436999716010020080000200240000800408004011802011009910010080000800001008000002108000100680001121051107171211800378000080000801008018280170800418004180041
8020480040620000000012001080025883251601008010080000801008000041797033758824080015800408004069924369997160100200800002002400008004080040118020110099100100800008000010080000021080001004800011210511011171212800378000080000801008004180041800418004180041
8020480040621000000004010800258832516010080100800008010080000417970337588240800158004080040699243699971601002008000020024000080040800401180201100991001008000080000100800000008000110980000000511011171314800378000080000801008004180041800418004180041
8020480040620000000012400080025880251601008010080000801008000041797033758824080015800408004069924369997160100200800002002400008004080040118020110099100100800008000010080000021080000006800011210511013171214800378000080000801008004180041800418004180041
802048004062000000001220108002508325160100801008000080100800004179703375882408001580040800406992436999716010020080000200240000800408004011802011009910010080000800001008000000080001004800011210511012171212800378000080000801008004180041800418004180041
8020480040620000000004010800250812516010080100800008010080000417970337588240800158004080040699243699971601002008000020024000080040800401180201100991001008000080000100800000008000030680001121051107171213800378000080000801008004180041800418004180041
8020480040621000000000000800258012516010080100800008010080000417970337588240800158004080040699243699971601002008000020024000080040800401180201100991001008000080000100800000210800010008000100051106171213800378000080000801008004180041800418004180041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f22243a3f46494f5051schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696b6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)7bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? ldst retires (ed)? int retires (ef)f5f6f7f8fd
8002580040621000000001008002588002516001080010800008001080000417864537588240800150800408004069946037002016001002080000202400008004080040118002110910108000080000108000001700800010008000111700005020331633338011580000080000800108004180041800418004180041
800248004062000000002000800258800251600108001080000800108000041786453758824080015080040800406994603700201600100208000020240000800408004011800211091010800008000010800000000800010038000011700005020131625348003780000080000800108004180041800418004180041
800248004062100000000000800250810251600108001080000800108000041786453758824080015080040800406994603700201600100208000020240000800408004011800211091010800008000010800000000800000038000111700005020311633338003780000080000800108004180041800418004180041
800248004062000000000000800250830251600108001080000800108000041786453758824080015080040800406994603700201600100208000020240000800408004011800211091010800008000010800000000800000038000021700005020321632328003780000080000800108004180041800418004180041
8002480040621000000041008002508202516001080010800008001080000417862137588240800150800408004069946037002016001002080000202400008004080040118002110910108000080000108000772501800080188000182671005020261632328003780000080000800108004180041800418004180041
800248004062011100001210180025111120251600108001080000800108000041786213758824080145080407802597001201670127160293020802402024048080152800951180021109101080000800001080008725008000810178000182571005036321632148003780000080000800108004180041800418004180041
800248004062010010009001800259118025160010800108000080010800004178621375882408001508004080040699460370020160010020800002024000080040800401180021109101080000800001080007725008000802118000182571005020321612328003780000080000800108004180041800418004180041
800248004062011000002000800258030251600108001080000800108000041786453758824080015080040800406994603700201600100208000020240000800408004011800211091010800008000010800000000800000008000101700005020321613328003780000080000800108004180041800418004180041
8002480040621000000001008002580002516001080010800008001080000417864537588240800150800408004069946037002016001002080000202400008004080040118002110910108000080000108000001700800010038000111800005020141632138003780000080000800108004180041800418004180041
8002480040620000000040008002580102516001080010800008001080000417864537588240800150800408004069946037002016001002080000202400008004080040118002110910108000080000108000001700800010018000111700005020321613328003780000080000800108004180041800418004180041