Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, post-index, 1 reg, 4H)

Test 1: uops

Code:

  st1 { v0.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f22233a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
610052871323211011180000100484728324102362220001000100010001000500050008159792821328861310200010003000284932855811610011000100010022311001021100010110132259634690631499382110731973817193737281241000153401274214286100010002850228702285292870128888
6100428700230118001110002004766282630023883200010001000100010015000500081619328096287663102000100030002848028553116100110001000100322110010111000101001322498056927321310312106932963817173439281991000155881303714688100010002892028856288362874328735
610042864223011200121000100477928297002380320001000100010001000500050007159442808528620310200010003000286022846111610011000100010031311001001100013110133989532686430849372120432753811103735282711000153171302414363100010002867028592287732868828626
610042863023111111191006100466128359102376120001000100010001000500050006159322820628861327200010003000288372885911610011000100010013421003021100114100132479270694730757402136332693821103939283151000156401290914845100010002891028833290082896228948
61004290102321121113110010046862863622239652000100010001000100050005000161595928275290893102000100030002885329068116100110001000100113110030045110001010148131799527692531156382123732413812183437285291000157071313314732100010002887728798292602889628946
6100428943231114221021317128600461828573002389320021000100010001000500050007159922810728841310200010003000288062876011610011000100010012201001061100013110133249396690630938372125933143750193940283091000155791300514374100010002884729009289252884928825
610042884123211411151009100475828495202386120001000100010001000500050001116048281722894431020001000300028814289071161001100010001002241100110221100012130132629315688231589412118132803810313232282201001156981301914793100010002900828996290242897328866
6100429037233113221023114117800461228396002392020001000100110001001500050001215986281902908531020001002300628766291121161001100010001005120100303801100013130129859289682930734392133532103815183441285361001158121328914528100010002921629110290512915829020
6100429012234114221102026489004713285350023962200010001000100010005000500081597228138290828102000100030002916029024116100110001000100322110010111000131101320293876989315913402116132553813163335282581001154041297614644100010002880728856288162909229296
6100428972231113101610001104740289440023875200010001000100010005000500011159822832728879327200010003000286942864311610011000100010021211001021100010130129168944678429998362167130903818443438291561008159911316114606100010002967229596294852972328915

Test 2: throughput

Count: 8

Code:

  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0f18191e1f23243a3f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
80205800926210011000102200180025884425160164801318002580186800004178218375882418005480040800406992487003016010020080000200240000800918004021802011009910010080000800001008000001708000100080001217511221712800378000080000801008004180041800418004180041
80204800406211010000020018002588125160100801008000080100800004179703375882418001580040800406992436999716010020080000200240000800408004011802011009910010080000800001008000001708000100080001117511221721800378000080000801008004180041800418004180041
8020480040620100000002001800258032516010080100800008010080000417970337588241800158004080040699243699971601002008000020024000080040800401180201100991001008000080000100800000008000000080001117511011712800378000080000801008004180041800418004180041
80204800406201000000000018002580132160100801008000080100800004179703375882418001580040800406992436999716010020080000200240000800408004011802011009910010080000800001008000001708000110180001117511021712800378000080000801008004180041800418004180041
80204800406211010000001008002580025160100801008000080100800004179703375882418001580040800406992436999716010020080000200240000800408004011802011009910010080000800001008000001708000000080001117511021722800378000080000801008004180041800418004180041
80204800406210010000000018002588325160100801008000080100800004179703375882418001580040800406992436999716010020080000200240000800408004011802011009910010080000800001008000001708000100080001017511211721800378000080000801008004180041800418004180041
8020480040620101000004001800258032516010080100800008010080000417970337588241800158004080040699243699971601002008000020024000080040800401180201100991001008000080000100800000008000010380001017511021722800378000080000801008004180041800418004180041
80204800406211000000040008002588025160100801008000080100800004179703375882418001580040800406992436999716010020080000200240000800408004011802011009910010080000800001008000001708000000680001117511211722800378000080000801008004180041800418004180041
802048004062100100001220008002588025160100801008000080100800004179703375882418001580040800406992436999716010020080000200240000800408004011802011009910010080000800001008000001708000100080001017511221712800378000080000801008004180041800418004180041
802048004062100100001240018002508025160100801008000080100800004179703375882418001580040800406992436999716010020080000200240000800408004011802011009910010080000800001008000001708000220380001117511021712800378000080000801008004180041800418004180041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f2223243a3f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? ldst retires (ed)? int retires (ef)f5f6f7f8fd
80025800406431000000600018002511802516001080030800008008980067417864537598938001538004080040699653700201600102080000202402738007680040218002110910108000080000108000001790800010038000002570050209169880037800001780000800108004180041800418004180041
8002480040620000000120100080025101042516001080010800008001080000417862137588248001508004080040699463700201600102080000202400008004080040118002110910108000080000108000001700800010038000110000502091610680037800001780000800108004180041800418004180041
800248004062111110001210018002588325160010800108000080010800004178645375882480015080040800406994637002016001020800002024000080040800401180021109101080000800001080000017008000110380000100005020101610108003780000080000800108004180041800418004180041
800248004062010010009000180025911425160010800108000080010800004178621375882480015080040800406994637002016001020800002024000080040800401180021109101080000800001080000017008000100380000117000502091611680037800001780000800108004180041800418004180041
8002480040620101000090001800251111425160010800108000080010800004178621375882480015080040800406994637002016001020800002024000080040800401180021109101080000800001080007725008000800118008982570050201016111680037800001780000800108004180041800418004180041
8002480040620100000090001800251111425160010800108000080010800004178621375882480015080040800406994637002016001020800002024000080040800401180021109101080000800001080008725008000700148000182573050201116111080037800002080000800108004180041800418004180041
80024800406200000000200008002511113251600108001080000800108000041786453758824800150800408004069946370020160010208000020240000800408004011800211091010800008000010800077250080008008800018257005020111610980037800001780000800108004180041800418004180041
8002480040620000000020010800251111425160010800108000080010800004178621375882480015080040800406994637002016001020800002024000080040800401180021109101080000800001080000000080001003800010000050209169980037800001980000800108004180041800418004180041
80024800406201100000200008002511118251600108001080000800108000041786213758824800150800408004069971370020160010208000020240000800408004011800211091010800008000010800000170080000003800011000050209169880037800001780000800108004180041800418004180041
8002480040620101100012000180025880251600108001080000800108000041786453758824800150800408004069946370020160010208000020240000800408004011800211091010800008000010800077250080008038800008257005020916101080037800001780000800108004180041800418004180041