Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, post-index, 1 reg, 4S)

Test 1: uops

Code:

  st1 { v0.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f223a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafl1d cache miss st nonspec (c0)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
6100529418236410010010004664288660024447200010001000100010005000500011001597928414293763102000100030002919729302116100110001000100203010000001000000132909537698731630442174033433820124346285891000163551332315101100010002953529505296432959029745
6100429554238031010000104581288370124539200010001000100010005000500030015945283612936631020001000300029251292091161001100010001000000100000211000300132919410693731620352164031603832113533286591000159951373215218100010002934529390292722927429336
610042930823502003000000464628777002437920001000100010001000500050001001595928540292553102000100030002914029285216100110001000100302010000001000200131679595697431200402174132393830143647284941000164121352715192100010002935829350293462922729383
61004293642360200300013201468528869002441420001000100010001000500050003001595228377293743102000100030002915929227116100110001000100022210000001000000130909419691531763402168032373830114338286471002163321355014982100010002931829505295192943429460
610042941823603004000010482028921002444720001000100010001000500050005001596628643294123102000100030002926529250116100110001000100000010000001000200134439521697231131402185733313826144346288931000162441367215139100010002973829588295732978029585
6100429743236040051001320047142897600246342000100010001000100050005000000159742863829515310200010003000293072935811610011000100010000301000003851000300131349535700831741422186533923832144141287951000162551377815228100010002952429574294702961929457
610042962023902014100000463028865002436820001000100010001000500050002001593228549294513102000100030002931829252116100110001000100003010000001000220131709386700031300402168933223819164144287391000159991359415103100010002951129408293262933829534
61004294032370300200013210464528886002458920001000100010001000500050006001596328536294003102000100030002940329255116100110001000100000010011001000000133769337692131102412182932473771194442287211000162481370115211100010002950329428293282933529596
610042935123500003100000469328936012435620001000100010001000500050000001595528654293723102000100030002928429220116100110001000100002010000001000300132119419697231801432174832793827124345287601000161251342715228100010002947229510294952949929554
61004294322370300100000147642885701243542002100010001000100050005000200159532872929481329200010003000292062935811610011000100010000201000100100000013409947669713186042218193260382993838286751000163621337915177100010002946229435293882942629442

Test 2: throughput

Count: 8

Code:

  st1 { v0.4s }, [x6], x8
  st1 { v0.4s }, [x6], x8
  st1 { v0.4s }, [x6], x8
  st1 { v0.4s }, [x6], x8
  st1 { v0.4s }, [x6], x8
  st1 { v0.4s }, [x6], x8
  st1 { v0.4s }, [x6], x8
  st1 { v0.4s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f2223243f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5e60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst simd alu (9a)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafldst x64 uop (b1)bcl1d cache miss st nonspec (c0)c2branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
8020580040620000004000800258832516010080100800008010080000417970337588240080015800408004069924369997160100200800002002400008004080040118020110099100100800000800001008000000080001000800010017000511011711800378000080000801008004180041800418004180041
80204800406210000000008002580025160100801008000080100800004179703375882400800158004080040699243699971601002008000020024026480040800401180201100991001008000008000010080000017080001100800010117000511011711800378000080000801008004180041800418004180041
80204800406200000040008002588025160100801008000080100800004179703375882400800158004080040699243699971601002008000020024000080040800401180201100991001008000008000010080000217080001100800010117000511011711800378000080000801008004180041800418004180041
80204800406210000020008002580025160100801008000080100800004179703375882400800158004080040699243699971601002008000020024000080040800401180201100991001008000008000010080000017080000003800010017000511011731800378000080000801008009380041800418004180041
80204800406200000940008002588325160100801008000080100800004179703375882400800158004080090699243699971601002008000020024000080040800401180201100991001008000008000010080000020080001001800230117000511011711800378000080000801008004180041800418004180041
80204800406430000020008002588025160100801008000080100800004179703375882400800158004080040699243699971601002008000020024000080040800401180201100991001008000008000010080000017080001104800010117000511011711800378000080000801008004180041800418004180041
8020480040643000002000800258032516010080100800008010080000417970337588240080024800408004069924369997160100200800002002400008004080040118020110099100100800000800001008000001708000110736800010117000511011711800378000080000801008009280041800418004180041
80204800406430000040008002588325160100801008002580100800004179703375882400800158004080040699243699971601002008000020024000080040800911180201100991001008000008000010080000017080001003800010119000511011711800378000080000801008004180041800418004180041
80204800406420000000008002588025160100801008000080100800004179703375993900800158004080040699248270743160100200800002002400008004080040118020110099100100800000800001008000001708000100380001010000511012511800378000080000801008004180041800418004180041
802048004064300000900008002508025160100801008000080100800004179703375882400800158004080040699243699971601002008007820024000080040800401180201100991001008000008000010080000017080001303800010017000511011711800378000080000801008009080041800418004180041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f233f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2branch call indir mispred nonspec (ca)cdcfd5map dispatch bubble (d6)dadbddfetch restart (de)e0? int output thing (e9)ea? ldst retires (ed)? int retires (ef)f5f6f7f8fd
80025800406211000000002080025883251600108001080000800128000041786453758824080015800408004069946370020160010208000020240000800408004011800211090101080000800001080000021080001001800011210005020816009118003780000080000800108004180041800418004180041
80024800406200000000013220800258802516001080010800008008380000417864537588240800158004080040699463700201633972080000202400008004080040218002110901010800008000010800240008000100380001121000502081600898003780000080000800108004180041800418004180041
800248004064300001000040800250802516001080010800008001080000417864537588240800158004080040699463700201600102080000202400008004080040118002110901010800008000010800000210800000008000110000502091602788003780000080000800108004180041800418004180041
8002480040620000000009008002588033160010800388000080010800004178645375882408001580040800406994637002016001020800002024000080040800401180021109010108000080000108000002108000110149480000121000502071602788003780000080000800108004180346803438034480041
8002480040643000000003040800258161980955162564813088115083544830364144198380770408189382442824567083120971467166925208000020240000800408004011800211090101080000800001080000021080001003800011210131502091602688003780000080000800108007780041800418004180041
8002480040600000000000408002588025160010800108000080010800004178645375882408001580040800406994637002016001020800002024000080040800401180021109010108000080000108000002108000110480001121000502071601998003780000080000800108004180041800418004180041
80024800406000000000002080025880251600108001080000800108000041786453760324080015800408004069946370020160010208000020240000800408004011800211090101080000800001080000021080001104800011210005020816011878003780000080000800108004180041800418004180041
8002480040641000000000008002588025160010800108000080010800004178645375882408001580040800406994637002016001020800002024000080040800401180021109010108000080000108000001708000000380001117000502071620878003780000080000800108004180041800418004180041
800248004060000000000000800258802516001080010800008001080000417864537588240800158004080040699463700201600102080000202400008004080040118002110901010800008000010800000170800011068000110000503671600878003780000080000800108004180041800418004180041
80024800406200000000012208002588025160010800108000080010800004177866375882408001580040800406996437002016001020800002024000080040800401180021109010108000080000108000001708000000680000117000502081600998003780000080000800108004180041800418004180041