Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st1 { v0.1d, v1.1d }, [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 3.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 23 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6b | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
62006 | 29219 | 234 | 0 | 22 | 0 | 0 | 20 | 0 | 0 | 0 | 135 | 89 | 1 | 0 | 4596 | 28757 | 1 | 1 | 18075 | 3000 | 1001 | 1002 | 1001 | 1000 | 1000 | 1000 | 5000 | 10940 | 8016 | 10 | 21698 | 0 | 28704 | 29077 | 17 | 29 | 3003 | 1002 | 1000 | 3003 | 2006 | 28984 | 29108 | 2 | 1 | 61001 | 1000 | 1000 | 1002 | 4 | 2 | 2 | 1005 | 0 | 0 | 625 | 1001 | 0 | 0 | 0 | 2 | 0 | 13174 | 9398 | 6899 | 3168 | 3 | 51 | 20436 | 3253 | 3813 | 16 | 49 | 58 | 28553 | 1005 | 15737 | 12953 | 14091 | 1000 | 1000 | 1000 | 29082 | 29110 | 29092 | 29144 | 29047 |
62004 | 29008 | 234 | 0 | 20 | 0 | 1 | 16 | 1 | 1 | 2 | 279 | 176 | 1 | 0 | 4628 | 29044 | 0 | 0 | 18284 | 3003 | 1001 | 1001 | 1002 | 1000 | 1001 | 1002 | 5005 | 10929 | 8000 | 2 | 21804 | 0 | 28959 | 29289 | 14 | 48 | 3000 | 1000 | 1002 | 3006 | 2002 | 29230 | 29178 | 3 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 2 | 1 | 1000 | 1 | 0 | 4 | 1000 | 0 | 2 | 0 | 0 | 0 | 13281 | 9328 | 6896 | 3122 | 13 | 48 | 20572 | 3323 | 3818 | 20 | 47 | 51 | 28667 | 1003 | 15921 | 13048 | 14298 | 1000 | 1000 | 1000 | 29150 | 29830 | 29350 | 29217 | 29413 |
62004 | 29177 | 233 | 0 | 18 | 0 | 0 | 20 | 0 | 0 | 0 | 258 | 11 | 0 | 1 | 4895 | 28890 | 0 | 0 | 18013 | 3000 | 1000 | 1001 | 1000 | 1000 | 1001 | 1000 | 5000 | 10908 | 8000 | 7 | 21754 | 0 | 28624 | 29141 | 3 | 10 | 3000 | 1000 | 1003 | 3000 | 2000 | 28721 | 28909 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 1 | 2 | 0 | 1001 | 4 | 0 | 7 | 1000 | 0 | 0 | 0 | 0 | 2293 | 13328 | 9543 | 6890 | 3216 | 9 | 53 | 20186 | 3261 | 3820 | 13 | 47 | 49 | 28218 | 1000 | 15720 | 12707 | 13754 | 1000 | 1000 | 1000 | 28726 | 28833 | 28982 | 28867 | 28873 |
62004 | 28774 | 231 | 0 | 19 | 0 | 0 | 20 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4563 | 29462 | 0 | 0 | 18339 | 3033 | 1009 | 1008 | 1005 | 1008 | 1007 | 1008 | 5040 | 11041 | 8040 | 0 | 22013 | 0 | 29212 | 29436 | 68 | 249 | 3024 | 1009 | 1012 | 3027 | 2018 | 29555 | 29429 | 17 | 1 | 61001 | 1000 | 1000 | 1011 | 4 | 0 | 0 | 1016 | 0 | 3 | 6636 | 1011 | 0 | 0 | 1 | 0 | 0 | 13498 | 9130 | 6888 | 3110 | 6 | 50 | 20307 | 3157 | 3817 | 21 | 45 | 48 | 28225 | 1000 | 15458 | 12742 | 13807 | 1000 | 1000 | 1000 | 28673 | 28859 | 28725 | 28849 | 28672 |
62004 | 28670 | 222 | 0 | 21 | 0 | 0 | 25 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 4750 | 28628 | 0 | 0 | 17719 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10905 | 8000 | 4 | 21729 | 0 | 28539 | 28825 | 3 | 30 | 3000 | 1000 | 1000 | 3000 | 2000 | 28680 | 28630 | 1 | 1 | 61001 | 1000 | 1000 | 1001 | 0 | 0 | 3 | 1000 | 0 | 0 | 1 | 1000 | 0 | 0 | 0 | 0 | 0 | 13138 | 9388 | 6927 | 3132 | 10 | 58 | 20154 | 3133 | 3816 | 15 | 48 | 53 | 28266 | 1001 | 15636 | 12805 | 13655 | 1000 | 1000 | 1000 | 28775 | 28762 | 28816 | 28748 | 28853 |
62004 | 28728 | 223 | 0 | 18 | 0 | 0 | 18 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 4763 | 28649 | 0 | 0 | 17788 | 3000 | 1001 | 1000 | 1000 | 1000 | 1000 | 1000 | 5005 | 10905 | 8000 | 4 | 21727 | 0 | 28584 | 28872 | 9 | 30 | 3000 | 1000 | 1000 | 3000 | 2000 | 28631 | 28751 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 2 | 0 | 0 | 0 | 13292 | 9310 | 7029 | 3093 | 3 | 51 | 20286 | 3195 | 3821 | 20 | 58 | 50 | 28341 | 1000 | 15733 | 12827 | 13646 | 1000 | 1000 | 1000 | 28857 | 28943 | 28796 | 28881 | 28852 |
62004 | 28856 | 223 | 0 | 22 | 0 | 0 | 14 | 0 | 0 | 0 | 132 | 1 | 0 | 0 | 4681 | 28780 | 0 | 0 | 17898 | 3000 | 1000 | 1000 | 1000 | 1001 | 1000 | 1000 | 5000 | 10897 | 8000 | 6 | 21526 | 0 | 28537 | 28832 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28798 | 28744 | 2 | 1 | 61001 | 1000 | 1000 | 1002 | 7 | 0 | 1 | 1001 | 0 | 1 | 31 | 1000 | 0 | 0 | 1 | 1 | 0 | 13070 | 9259 | 6944 | 3101 | 6 | 51 | 20272 | 3214 | 3817 | 15 | 51 | 48 | 28288 | 1000 | 15448 | 12750 | 13730 | 1000 | 1000 | 1000 | 28870 | 28967 | 28847 | 28888 | 28789 |
62004 | 28825 | 223 | 0 | 24 | 1 | 0 | 20 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 4703 | 28763 | 0 | 0 | 17911 | 3003 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10908 | 8000 | 3 | 21745 | 0 | 28589 | 28706 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28730 | 28717 | 1 | 1 | 61001 | 1000 | 1000 | 1003 | 2 | 2 | 0 | 1001 | 0 | 1 | 1 | 1000 | 0 | 0 | 1 | 0 | 0 | 13191 | 9517 | 6907 | 3140 | 9 | 49 | 20234 | 3299 | 3823 | 12 | 51 | 53 | 28349 | 1000 | 15685 | 12918 | 13824 | 1000 | 1000 | 1000 | 28853 | 28852 | 28767 | 28929 | 28858 |
62004 | 28788 | 223 | 0 | 22 | 1 | 0 | 22 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 4706 | 28712 | 0 | 0 | 17758 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10902 | 8000 | 0 | 21699 | 0 | 28619 | 28958 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28819 | 28739 | 2 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 2 | 0 | 1002 | 0 | 0 | 1 | 1000 | 0 | 0 | 0 | 0 | 0 | 13154 | 9386 | 6892 | 3134 | 9 | 51 | 20262 | 3246 | 3819 | 15 | 54 | 51 | 28363 | 1000 | 15656 | 12649 | 13973 | 1000 | 1000 | 1000 | 28771 | 28727 | 28907 | 28828 | 28828 |
62004 | 28764 | 224 | 0 | 19 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 4657 | 28813 | 0 | 0 | 17793 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10901 | 8000 | 0 | 21774 | 0 | 28594 | 28719 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28707 | 28841 | 2 | 1 | 61001 | 1000 | 1000 | 1003 | 0 | 2 | 0 | 1000 | 0 | 3 | 0 | 1000 | 0 | 2 | 0 | 0 | 0 | 13282 | 9341 | 6905 | 3126 | 7 | 49 | 20290 | 3245 | 3822 | 20 | 51 | 49 | 28360 | 1000 | 15703 | 12644 | 13765 | 1000 | 1000 | 1000 | 28777 | 28848 | 28840 | 28791 | 28732 |
Count: 8
Code:
st1 { v0.1d, v1.1d }, [x6], x8 st1 { v0.1d, v1.1d }, [x6], x8 st1 { v0.1d, v1.1d }, [x6], x8 st1 { v0.1d, v1.1d }, [x6], x8 st1 { v0.1d, v1.1d }, [x6], x8 st1 { v0.1d, v1.1d }, [x6], x8 st1 { v0.1d, v1.1d }, [x6], x8 st1 { v0.1d, v1.1d }, [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 80040 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 276 | 7 | 0 | 0 | 2391 | 1 | 80025 | 11 | 0 | 75 | 25 | 242656 | 80100 | 84257 | 80000 | 80100 | 80000 | 80000 | 4358994 | 3758848 | 644423 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240448 | 200 | 80000 | 80000 | 200 | 240000 | 160240 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80007 | 7 | 0 | 0 | 0 | 80008 | 1 | 1 | 14 | 80000 | 8 | 28 | 7 | 1 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80162 |
160204 | 80040 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 | 0 | 3056 | 1 | 80025 | 11 | 11 | 1 | 25 | 243527 | 80100 | 80161 | 80000 | 80100 | 80000 | 80000 | 4358990 | 3758848 | 646657 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80008 | 9 | 25 | 0 | 0 | 80008 | 0 | 0 | 1103 | 80001 | 8 | 25 | 7 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 12 | 12 | 0 | 0 | 116 | 1 | 80025 | 0 | 11 | 5 | 25 | 241739 | 80100 | 82587 | 80000 | 80100 | 80116 | 80000 | 4358990 | 3758848 | 646157 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80008 | 10 | 25 | 0 | 0 | 80008 | 0 | 0 | 8 | 80001 | 8 | 25 | 7 | 1 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 132 | 7 | 0 | 0 | 2420 | 1 | 80133 | 11 | 11 | 2 | 25 | 245263 | 80100 | 82562 | 80000 | 80100 | 80000 | 80000 | 4358990 | 3758848 | 644916 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240360 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80008 | 7 | 25 | 0 | 1 | 80008 | 0 | 1 | 7 | 80001 | 8 | 25 | 7 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80142 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80161 | 80041 |
160204 | 80040 | 620 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 2472 | 1 | 80025 | 11 | 10 | 2 | 25 | 244353 | 80100 | 81223 | 80000 | 80100 | 80000 | 80000 | 4358990 | 3758848 | 646589 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80007 | 7 | 25 | 0 | 0 | 80008 | 0 | 0 | 8 | 80001 | 7 | 25 | 7 | 1 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 132 | 7 | 0 | 0 | 5163 | 1 | 80025 | 9 | 11 | 1 | 25 | 245209 | 80100 | 80161 | 80000 | 80100 | 80000 | 80000 | 4358990 | 3758848 | 645983 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80008 | 8 | 0 | 0 | 0 | 80008 | 0 | 0 | 8 | 80001 | 7 | 25 | 7 | 0 | 0 | 5110 | 1 | 16 | 2 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 2051 | 1 | 80147 | 11 | 10 | 2 | 25 | 245263 | 80100 | 82536 | 80000 | 80100 | 80116 | 80000 | 4358990 | 3758848 | 649185 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80067 | 9 | 0 | 0 | 1 | 80008 | 1 | 0 | 8 | 80000 | 8 | 25 | 7 | 1 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 2577 | 1 | 80025 | 10 | 11 | 2 | 25 | 242266 | 80100 | 84267 | 80000 | 80100 | 80000 | 80000 | 4358994 | 3758848 | 655525 | 0 | 80015 | 3 | 80040 | 80040 | 59924 | 3 | 59998 | 240440 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80007 | 7 | 0 | 0 | 1 | 80068 | 0 | 0 | 8 | 80000 | 7 | 25 | 7 | 0 | 0 | 5110 | 1 | 25 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 12 | 9 | 0 | 0 | 137 | 1 | 80025 | 10 | 11 | 6 | 25 | 240222 | 80100 | 80118 | 80060 | 80100 | 80000 | 80000 | 4358990 | 3758848 | 646157 | 0 | 80015 | 0 | 80163 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80007 | 7 | 25 | 0 | 0 | 80007 | 0 | 0 | 11 | 80001 | 7 | 0 | 7 | 0 | 1 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 2173 | 1 | 80025 | 11 | 11 | 2 | 25 | 242148 | 80100 | 80158 | 80000 | 80100 | 80000 | 80000 | 4358990 | 3758848 | 643892 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240440 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80008 | 7 | 25 | 0 | 1 | 80008 | 0 | 0 | 11 | 80000 | 8 | 25 | 7 | 1 | 0 | 5110 | 2 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 37 | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 61 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | 91 | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | atomic or exclusive succ (b3) | b6 | bc | l1d cache miss st nonspec (c0) | c2 | cf | d0 | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 4 | 0 | 0 | 5633 | 80025 | 8 | 8 | 0 | 25 | 244704 | 80010 | 84697 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 654081 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 0 | 0 | 0 | 80001 | 2 | 0 | 1 | 80001 | 0 | 0 | 1 | 0 | 0 | 5022 | 5 | 0 | 2 | 16 | 2 | 2 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 80025 | 8 | 8 | 3 | 25 | 241167 | 80010 | 80692 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 657081 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 21 | 0 | 0 | 80000 | 1 | 0 | 3 | 80001 | 0 | 0 | 1 | 21 | 0 | 5020 | 0 | 0 | 2 | 16 | 2 | 2 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80179 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 1296 | 80025 | 8 | 0 | 0 | 25 | 240590 | 80010 | 85637 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 646153 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 24 | 0 | 0 | 80001 | 1 | 0 | 0 | 80001 | 0 | 0 | 1 | 21 | 4 | 5022 | 5 | 0 | 2 | 16 | 2 | 2 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 918 | 80025 | 0 | 0 | 3 | 25 | 244704 | 80010 | 85692 | 80000 | 80126 | 80000 | 80000 | 4358429 | 3758848 | 654085 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80062 | 0 | 21 | 0 | 0 | 80000 | 0 | 0 | 0 | 80001 | 0 | 0 | 1 | 21 | 0 | 5020 | 5 | 0 | 2 | 16 | 2 | 2 | 80037 | 80092 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80162 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 4694 | 80025 | 8 | 0 | 0 | 25 | 240590 | 80010 | 83757 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 642772 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 21 | 0 | 0 | 80001 | 1 | 0 | 1 | 80001 | 0 | 0 | 1 | 21 | 0 | 5020 | 5 | 0 | 2 | 16 | 2 | 2 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80162 | 80041 | 80041 |
160024 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 33 | 0 | 0 | 0 | 694 | 80025 | 8 | 8 | 0 | 25 | 244704 | 80010 | 80580 | 80000 | 80010 | 80000 | 80000 | 4360801 | 3758848 | 640019 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 0 | 1 | 80001 | 0 | 0 | 1 | 21 | 0 | 5020 | 5 | 0 | 2 | 16 | 2 | 2 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 138 | 4 | 0 | 0 | 1262 | 80025 | 8 | 8 | 71 | 25 | 241392 | 80010 | 80018 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 654085 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 0 | 1 | 80061 | 0 | 0 | 1 | 21 | 0 | 5020 | 5 | 0 | 2 | 16 | 2 | 2 | 80141 | 80000 | 80000 | 80000 | 80010 | 80041 | 80167 | 80041 | 80162 | 80041 |
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