Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st1 { v0.2s, v1.2s }, [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 3.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 23 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 60 | 61 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
62006 | 29643 | 237 | 4 | 1 | 2 | 0 | 0 | 5 | 1 | 1 | 0 | 6 | 1 | 0 | 0 | 4687 | 29144 | 1 | 1 | 18385 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10894 | 8000 | 10 | 0 | 0 | 21738 | 29203 | 29490 | 3 | 10 | 3000 | 1001 | 1000 | 3000 | 2000 | 29450 | 29557 | 1 | 1 | 61001 | 1000 | 1000 | 1001 | 2 | 0 | 0 | 1001 | 0 | 1 | 1 | 1001 | 1 | 3 | 1 | 1 | 0 | 13139 | 9434 | 6903 | 3161 | 0 | 66 | 20903 | 3284 | 3816 | 19 | 54 | 55 | 28778 | 1000 | 16545 | 13491 | 14483 | 1000 | 1000 | 1000 | 29512 | 29513 | 29450 | 29259 | 29445 |
62004 | 29494 | 236 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 4608 | 29290 | 0 | 0 | 18500 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10910 | 8000 | 9 | 0 | 0 | 21738 | 29197 | 29484 | 7 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29331 | 29413 | 1 | 1 | 61001 | 1000 | 1000 | 1001 | 3 | 3 | 1 | 1001 | 0 | 2 | 1 | 1000 | 1 | 3 | 1 | 2 | 0 | 13297 | 9461 | 6875 | 3178 | 0 | 50 | 20868 | 3402 | 3811 | 10 | 53 | 51 | 28905 | 1000 | 16149 | 13234 | 14324 | 1000 | 1000 | 1000 | 29466 | 29608 | 29599 | 29516 | 29316 |
62004 | 29514 | 236 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 4626 | 29272 | 0 | 0 | 18590 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10903 | 8000 | 11 | 0 | 0 | 21685 | 29289 | 29415 | 11 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29371 | 29404 | 1 | 1 | 61001 | 1000 | 1000 | 1003 | 2 | 2 | 1 | 1001 | 0 | 1 | 401 | 1000 | 1 | 3 | 1 | 0 | 0 | 13091 | 9175 | 6951 | 3171 | 0 | 51 | 20785 | 3269 | 3814 | 18 | 55 | 58 | 28716 | 1000 | 16171 | 13150 | 14708 | 1000 | 1000 | 1000 | 29355 | 29439 | 29478 | 29371 | 29468 |
62004 | 29486 | 236 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 4749 | 29235 | 0 | 0 | 18525 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10934 | 8000 | 10 | 0 | 0 | 21702 | 29048 | 29470 | 8 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29424 | 29486 | 1 | 1 | 61001 | 1000 | 1000 | 1003 | 2 | 3 | 1 | 1001 | 0 | 1 | 386 | 1001 | 1 | 3 | 1 | 1 | 0 | 13276 | 9354 | 6925 | 3217 | 0 | 52 | 20824 | 3317 | 3811 | 11 | 56 | 50 | 28765 | 1000 | 16127 | 13546 | 14506 | 1000 | 1000 | 1000 | 29419 | 29507 | 29427 | 29469 | 29469 |
62004 | 29515 | 236 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 4721 | 29237 | 1 | 1 | 18461 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1001 | 5000 | 10906 | 8000 | 6 | 0 | 0 | 21721 | 29113 | 29435 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29389 | 29433 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 1 | 3 | 1 | 1001 | 0 | 1 | 1 | 1000 | 1 | 0 | 1 | 1 | 0 | 13225 | 9396 | 6924 | 3133 | 0 | 51 | 20963 | 3254 | 3810 | 14 | 62 | 51 | 28848 | 1000 | 16001 | 13478 | 14607 | 1000 | 1000 | 1000 | 29631 | 29515 | 29681 | 29578 | 29647 |
62004 | 29657 | 238 | 2 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 4672 | 29285 | 1 | 0 | 18375 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10908 | 8000 | 10 | 0 | 0 | 21714 | 29113 | 29525 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29272 | 29387 | 1 | 1 | 61001 | 1000 | 1000 | 1003 | 1 | 3 | 1 | 1001 | 0 | 0 | 1 | 1000 | 1 | 0 | 1 | 0 | 0 | 13284 | 9335 | 6933 | 3136 | 0 | 46 | 20800 | 3339 | 3810 | 17 | 53 | 55 | 28707 | 1000 | 16129 | 13137 | 14341 | 1000 | 1000 | 1000 | 29268 | 29330 | 29358 | 29288 | 29386 |
62004 | 29327 | 235 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 4578 | 29287 | 0 | 0 | 18295 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10901 | 8000 | 6 | 0 | 0 | 21744 | 29110 | 29227 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29281 | 29204 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 3 | 1 | 1001 | 1 | 1 | 1 | 1000 | 1 | 0 | 1 | 0 | 0 | 13222 | 9341 | 6938 | 3203 | 0 | 55 | 20682 | 3189 | 3807 | 11 | 50 | 48 | 28797 | 1000 | 16296 | 13299 | 14355 | 1000 | 1000 | 1000 | 29559 | 29445 | 29455 | 29366 | 29369 |
62004 | 29358 | 238 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 144 | 1 | 0 | 0 | 4608 | 29238 | 0 | 0 | 18296 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10900 | 8000 | 6 | 1 | 0 | 21737 | 28980 | 29349 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29428 | 29510 | 1 | 1 | 61001 | 1000 | 1000 | 1001 | 2 | 3 | 2 | 1001 | 0 | 2 | 1 | 1000 | 1 | 3 | 1 | 2 | 0 | 13185 | 9238 | 6895 | 3138 | 1 | 61 | 20686 | 3294 | 3817 | 15 | 60 | 55 | 28746 | 1000 | 16202 | 13382 | 14408 | 1000 | 1000 | 1000 | 29382 | 29444 | 29467 | 29443 | 29279 |
62004 | 29376 | 236 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4587 | 29232 | 0 | 0 | 18426 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10908 | 8000 | 3 | 0 | 0 | 21759 | 29139 | 29421 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29300 | 29298 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 0 | 2 | 1001 | 0 | 1 | 1 | 1000 | 1 | 3 | 1 | 1 | 0 | 13327 | 9347 | 6931 | 3191 | 0 | 55 | 20842 | 3376 | 3811 | 10 | 53 | 56 | 28764 | 1000 | 16002 | 13176 | 14358 | 1000 | 1000 | 1000 | 29484 | 29413 | 29394 | 29289 | 29472 |
62004 | 29476 | 238 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 6 | 1 | 0 | 0 | 4757 | 29040 | 0 | 0 | 18421 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10905 | 8000 | 10 | 0 | 0 | 21724 | 29102 | 29370 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29303 | 29438 | 1 | 1 | 61001 | 1000 | 1000 | 1003 | 3 | 3 | 0 | 1001 | 0 | 1 | 1 | 1000 | 1 | 0 | 1 | 1 | 0 | 13165 | 9498 | 6933 | 3163 | 0 | 55 | 20802 | 3362 | 3807 | 11 | 61 | 51 | 28609 | 1000 | 15984 | 13474 | 14204 | 1000 | 1000 | 1000 | 29339 | 29446 | 29629 | 29395 | 29437 |
Count: 8
Code:
st1 { v0.2s, v1.2s }, [x6], x8 st1 { v0.2s, v1.2s }, [x6], x8 st1 { v0.2s, v1.2s }, [x6], x8 st1 { v0.2s, v1.2s }, [x6], x8 st1 { v0.2s, v1.2s }, [x6], x8 st1 { v0.2s, v1.2s }, [x6], x8 st1 { v0.2s, v1.2s }, [x6], x8 st1 { v0.2s, v1.2s }, [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 3475 | 0 | 80025 | 8 | 8 | 0 | 25 | 242329 | 80100 | 81969 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 652906 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 28 | 0 | 80001 | 0 | 2 | 2 | 80001 | 1 | 17 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80410 | 643 | 0 | 0 | 0 | 1 | 0 | 1794 | 2 | 0 | 0 | 1285 | 1 | 80025 | 8 | 0 | 3 | 25 | 244395 | 80100 | 80115 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3775546 | 643525 | 80225 | 0 | 80040 | 80319 | 60387 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 29 | 0 | 80001 | 2 | 0 | 4 | 80000 | 1 | 19 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 652 | 0 | 0 | 0 | 0 | 0 | 12 | 3 | 0 | 0 | 1160 | 0 | 80025 | 8 | 8 | 1 | 25 | 240213 | 80100 | 80096 | 80000 | 80100 | 80116 | 80000 | 4359014 | 3758848 | 673748 | 80015 | 0 | 80040 | 80040 | 59986 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 3 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80000 | 2 | 0 | 7 | 80001 | 1 | 0 | 0 | 0 | 5110 | 2 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80163 | 80041 |
160204 | 80161 | 642 | 0 | 1 | 0 | 1 | 0 | 21 | 4 | 0 | 0 | 117 | 0 | 80025 | 8 | 8 | 3 | 257 | 251549 | 82021 | 85161 | 80000 | 80100 | 80115 | 80000 | 4359014 | 3758848 | 647929 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80120 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 0 | 12 | 80002 | 1 | 21 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80163 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 644 | 0 | 0 | 0 | 0 | 0 | 141 | 4 | 0 | 0 | 5192 | 0 | 80025 | 8 | 8 | 71 | 25 | 242329 | 80191 | 81150 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3763084 | 640480 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240440 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80285 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 0 | 13 | 80002 | 1 | 21 | 0 | 0 | 5127 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80163 | 80163 | 80041 | 80041 |
160204 | 80040 | 647 | 0 | 1 | 1 | 0 | 0 | 21 | 92 | 0 | 0 | 3403 | 0 | 80025 | 8 | 8 | 1 | 25 | 240199 | 80100 | 85280 | 80000 | 80100 | 80000 | 80108 | 4359014 | 3758848 | 640378 | 80120 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 22 | 0 | 0 | 80001 | 2 | 0 | 24 | 80001 | 1 | 0 | 2 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 81369 | 80413 |
160204 | 80040 | 643 | 0 | 0 | 0 | 0 | 0 | 12 | 3 | 0 | 0 | 117 | 0 | 80025 | 8 | 8 | 3 | 25 | 245572 | 80100 | 84303 | 80000 | 80100 | 80000 | 80432 | 4363838 | 3763132 | 655318 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 60161 | 240100 | 200 | 80000 | 80120 | 200 | 240000 | 160240 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80061 | 1 | 0 | 437 | 80000 | 1 | 17 | 0 | 0 | 5110 | 2 | 16 | 1 | 2 | 80037 | 80183 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 643 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | 0 | 0 | 1216 | 0 | 80144 | 8 | 0 | 0 | 25 | 240186 | 80284 | 82309 | 80000 | 80100 | 80115 | 80000 | 4359014 | 3758848 | 652906 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80120 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80120 | 0 | 0 | 29 | 0 | 80000 | 1 | 0 | 2619 | 80001 | 0 | 17 | 4 | 0 | 5110 | 1 | 25 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80286 | 653 | 0 | 0 | 0 | 0 | 0 | 285 | 3 | 0 | 0 | 1979 | 0 | 80150 | 8 | 8 | 0 | 25 | 240217 | 80100 | 85174 | 80000 | 80100 | 80236 | 80000 | 4368534 | 3763084 | 640270 | 80015 | 0 | 80040 | 80160 | 59924 | 3 | 60081 | 240100 | 200 | 80000 | 80120 | 200 | 240000 | 160000 | 80162 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80000 | 0 | 0 | 245 | 80001 | 1 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 643 | 0 | 0 | 0 | 0 | 0 | 12 | 3 | 0 | 0 | 1454 | 0 | 80025 | 8 | 0 | 1 | 25 | 241580 | 80100 | 82673 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 655506 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 226 | 80001 | 1 | 17 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 23 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 80040 | 620 | 1 | 0 | 1 | 0 | 0 | 0 | 9 | 0 | 1656 | 1 | 80025 | 11 | 11 | 2 | 25 | 241389 | 80010 | 84738 | 80000 | 80010 | 80000 | 80000 | 4358417 | 3758848 | 654231 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 7 | 25 | 0 | 0 | 80008 | 0 | 1 | 8 | 80001 | 1 | 25 | 7 | 1 | 0 | 5020 | 2 | 16 | 3 | 3 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 20 | 1 | 80025 | 10 | 0 | 2 | 25 | 240031 | 80010 | 82822 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 654231 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 25 | 0 | 2 | 80008 | 0 | 1 | 11 | 80001 | 8 | 25 | 7 | 1 | 0 | 5020 | 3 | 16 | 2 | 2 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 12 | 7 | 0 | 5685 | 1 | 80025 | 8 | 11 | 2 | 25 | 240033 | 80010 | 81379 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 654083 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 25 | 0 | 0 | 80008 | 0 | 0 | 11 | 80001 | 7 | 25 | 7 | 0 | 0 | 5020 | 2 | 16 | 3 | 3 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 1619 | 3 | 80025 | 11 | 11 | 1 | 25 | 241781 | 80010 | 83758 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 640053 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 25 | 0 | 1 | 80000 | 1 | 2 | 14 | 80001 | 8 | 0 | 7 | 2 | 0 | 5020 | 2 | 16 | 3 | 3 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 0 | 0 | 0 | 0 | 12 | 9 | 0 | 1519 | 1 | 80025 | 9 | 10 | 6 | 25 | 244752 | 80010 | 81780 | 80000 | 80010 | 80000 | 80000 | 4358413 | 3758848 | 644170 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 7 | 25 | 0 | 0 | 80007 | 0 | 0 | 14 | 80001 | 7 | 0 | 7 | 0 | 0 | 5020 | 3 | 16 | 3 | 3 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 1 | 0 | 0 | 0 | 0 | 9 | 0 | 4698 | 1 | 80025 | 0 | 8 | 2 | 25 | 241163 | 80010 | 80027 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 651367 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 0 | 25 | 0 | 0 | 80008 | 0 | 0 | 8 | 80000 | 8 | 0 | 0 | 0 | 0 | 5020 | 3 | 16 | 2 | 2 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 1 | 1 | 0 | 0 | 0 | 12 | 0 | 5686 | 0 | 80025 | 11 | 11 | 2 | 25 | 240023 | 80010 | 84742 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 640051 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 17 | 0 | 1 | 80008 | 0 | 0 | 11 | 80000 | 8 | 25 | 7 | 0 | 0 | 5020 | 2 | 16 | 2 | 2 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
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