Firestorm: ST1 (multiple, post-index, 2 regs, 8H) measurements

Code:

  st1 { v0.8h, v1.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
62005	29678	238	0	0	13	0	0	6	0	0	0	0	1	0	0	0	4649	29005	2	2	24345	3000	1000	2000	1000	2000	5000	10000	17	0	0	16053	0	28555	29393	3	10	3000	2000	5000	29388	29350	1	1	61001	1000	1000	2003	3	6	2	2002	2	1	2	2004	0	4	0	0	0	13148	9574	6944	3153	7	52	20804	3301	3811	18	49	54	28685	1000	16332	13647	15197	2000	1000	29550	29434	29533	29446	29572
62004	29376	236	0	0	8	0	1	11	0	0	0	0	1	0	0	0	4707	28993	0	0	24336	3000	1000	2000	1000	2000	5000	10000	7	0	0	16112	0	28563	29553	3	10	3000	2000	5000	29372	29384	1	1	61001	1000	1000	2004	3	6	1	2002	2	0	222	2002	0	6	0	0	0	13280	9351	6953	3150	5	54	20909	3278	3807	15	53	52	28773	1000	16013	13875	15052	2000	1000	29523	29526	29446	29518	29557
62004	29770	237	0	0	7	0	1	11	0	3	1	132	265	0	0	0	4599	29056	0	0	24542	3000	1001	2002	1001	2004	5005	10098	8	0	0	16112	0	28649	29203	16	29	3003	2000	5000	29473	29389	2	1	61001	1000	1000	2002	5	0	0	2003	1	3	387	2004	4	4	0	0	0	13130	9128	6907	3157	4	55	20888	3315	3817	20	55	54	28840	1000	16427	13713	15078	2000	1000	29610	29794	29604	29700	29576
62004	29668	238	0	1	8	0	2	10	1	1	1	396	177	1	0	0	4641	28966	0	2	24565	3006	1001	2002	1000	2000	5005	10000	0	0	0	16055	0	28732	29769	3	10	3009	2000	5000	29350	29370	1	1	61001	1000	1000	2005	3	6	1	2002	5	1	11	2000	0	4	0	2	108	13289	9212	6914	3179	5	57	20846	3287	3816	17	58	49	28700	1001	15993	13603	15063	2000	1000	29445	29430	29587	29850	29432
62004	29429	236	0	0	10	0	0	8	0	0	0	0	0	1	0	0	4593	28917	0	2	24453	3000	1000	2000	1000	2000	5000	10010	0	0	0	16078	0	28590	29436	3	10	3000	2000	5000	29391	29336	1	1	61001	1000	1000	2003	2	4	2	2002	51	1	5	2000	0	4	0	0	424	13125	9444	6963	3158	2	51	20898	3292	3816	11	52	55	28642	1000	16125	13401	14846	2000	1000	29543	29421	29374	29476	29510
62004	29433	237	0	0	7	0	0	6	0	0	0	0	0	0	0	0	4688	29002	0	0	24299	3000	1000	2000	1000	2000	5000	10000	5	0	0	16071	0	28589	29382	3	10	3000	2014	5050	29357	29913	17	1	61001	1000	1000	2027	5	4	0	2010	58	0	7027	2010	0	0	0	0	0	13027	9021	6769	3091	2	53	20943	3116	3819	49	54	52	28961	1007	16387	13577	15088	2000	1000	30217	30534	30464	30338	30264
62004	29405	236	0	0	5	0	0	6	0	0	0	15	1	0	0	0	4669	28862	0	2	24333	3000	1000	2000	1000	2000	5000	10000	1	0	0	16063	0	28646	29258	3	10	3000	2000	5000	29148	29278	1	1	61001	1000	1000	2002	3	4	0	2002	8	1	2	2002	0	0	0	0	0	13134	9511	6974	3155	7	48	20774	3269	3815	18	49	48	28652	1000	16146	13413	15173	2000	1000	29290	29418	29399	29332	29455
62004	29336	227	0	1	8	0	1	11	1	0	0	0	1	0	0	0	4673	28962	0	0	24374	3000	1000	2000	1000	2000	5000	10000	4	0	0	16073	0	28605	29444	3	10	3000	2000	5000	29243	29290	1	1	61001	1000	1000	2003	2	6	0	2004	30	1	2	2000	0	4	0	4	0	13099	9520	6904	3146	3	51	20771	3312	3819	15	52	50	28551	1000	16176	13429	15058	2000	1000	29350	29332	29435	29326	29406
62004	29367	228	0	0	10	0	0	9	0	0	0	132	1	0	0	0	4654	28985	0	2	24367	3000	1000	2000	1000	2000	5000	10000	0	0	0	16062	0	28513	29412	3	10	3000	2000	5000	29116	29256	1	1	61001	1000	1000	2003	2	0	0	2002	56	0	2	2000	0	6	0	1	0	13122	9366	6899	3106	4	48	20767	3274	3812	16	42	46	28421	1000	16152	13552	14857	2000	1000	29234	29348	29292	29309	29308
62004	29326	226	0	0	6	0	0	8	0	0	0	0	1	0	0	0	4680	28870	2	2	24201	3000	1000	2000	1000	2000	5000	10000	5	0	0	16059	0	28399	29262	3	10	3000	2000	5000	29217	29021	1	1	61001	1000	1000	2003	3	0	1	2002	40	1	2	2002	0	6	0	0	0	13020	9373	6910	3138	5	43	20733	3298	3810	14	53	48	28606	1000	16039	13479	14945	2000	1000	29267	29356	29359	29327	29360

Count: 8

Code:

  st1 { v0.8h, v1.8h }, [x6], x8
  st1 { v0.8h, v1.8h }, [x6], x8
  st1 { v0.8h, v1.8h }, [x6], x8
  st1 { v0.8h, v1.8h }, [x6], x8
  st1 { v0.8h, v1.8h }, [x6], x8
  st1 { v0.8h, v1.8h }, [x6], x8
  st1 { v0.8h, v1.8h }, [x6], x8
  st1 { v0.8h, v1.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	80058	621	1	0	1	0	0	0	0	21	1	0	0	1	80025	16	16	0	25	240100	80100	160000	80100	160000	1080786	3679956	0	80022	0	80047	80059	59964	3	60008	240264	200	160000	200	400000	80059	80061	1	1	80201	100	99	100	100	80000	80000	100	160015	14	36	0	1	160016	0	0	18	160002	16	36	14	1	0	0	0	5110	1	16	1	1	80056	80000	160000	80100	80048	80059	80053	80060	80053
160204	80047	621	1	0	0	1	0	0	0	17	0	0	0	1	80043	0	16	0	25	240216	80100	160000	80100	160000	2040250	3680220	0	80033	0	80042	80058	59960	3	60017	240100	200	160000	200	400000	80178	80042	1	1	80201	100	99	100	100	80000	80000	100	160014	15	36	0	0	160016	0	0	14	160000	16	36	14	0	0	0	0	5110	1	16	1	1	80056	80000	160000	80100	80049	80048	80060	80061	80048
160204	80058	620	1	0	0	1	0	0	12	22	0	0	0	1	80043	16	16	6	25	240100	80100	160000	80100	160000	1160734	3679932	0	80034	0	80052	80052	59973	11	60005	240100	200	160000	200	400000	80047	80047	1	1	80201	100	99	100	100	80000	80000	100	160014	14	36	3	0	160016	1	1	30	160002	16	38	14	0	0	0	0	5110	1	16	1	1	80049	80000	160000	80100	80053	80048	80048	80060	80062
160204	80047	622	1	0	0	0	0	0	0	19	0	0	0	1	80032	16	16	3	25	240100	80100	160000	80100	160000	1000838	3679908	0	80033	0	80052	80047	59964	3	60010	240100	200	160000	200	400000	80047	80052	1	1	80201	100	99	100	100	80000	80000	100	160014	14	36	0	0	160016	0	1	18	160002	16	36	0	0	0	0	0	5110	1	16	1	1	80055	80000	160000	80100	80048	80049	80053	80060	80052
160204	80042	621	1	0	0	0	0	0	3	18	0	0	0	0	80037	16	0	1	25	240100	80100	160000	80100	160000	601186	3680220	0	80032	0	80058	80058	59960	3	60017	240100	200	160000	200	400000	80059	80059	1	1	80201	100	99	100	100	80000	80000	100	160014	14	36	0	0	160014	0	0	18	160002	16	36	14	0	0	0	0	5110	1	16	1	1	80049	80000	160000	80100	80053	80059	80061	80053	80059
160204	80059	621	1	0	1	0	0	0	0	19	0	0	0	1	80037	0	16	0	25	240100	80100	160000	80100	160000	601246	3680292	0	80022	0	80050	80047	59961	3	60005	240100	200	160000	200	400000	80060	80050	1	1	80201	100	99	100	100	80000	80000	100	160014	14	0	0	0	160016	0	0	17250	161802	2	36	0	0	0	0	0	5110	1	16	1	1	80057	80000	160000	80100	80048	80054	80059	80195	80060
160204	80059	620	1	0	0	0	0	0	0	21	0	0	0	1	80043	0	16	0	25	240100	80100	160000	80100	160000	1080794	3684720	0	80022	0	80047	80058	59963	3	60005	240100	200	160000	200	400000	80059	80059	1	1	80201	100	99	100	100	80000	80000	100	160014	17	36	0	0	160016	1	0	19	160002	16	34	14	0	0	0	0	5110	1	16	1	1	80050	80000	160000	80100	80053	80043	80051	80043	80062
160204	80183	621	0	1	0	0	0	1	12	14	0	0	0	1	80034	16	16	5	25	240100	80100	160000	80100	160000	2040250	3679424	0	80015	0	80048	80058	59955	3	60008	240100	200	160000	200	400000	80059	80040	1	1	80201	100	99	100	100	80000	80000	100	160014	14	36	0	0	160014	0	1	17	160002	16	0	14	0	0	0	0	5110	1	16	1	1	80048	80000	160000	80100	80052	80059	80061	80053	80060
160204	80057	621	1	0	1	0	0	0	0	19	0	0	0	1	80037	16	0	10	25	240100	80100	160000	80100	160000	1160726	3679692	0	80028	3	80058	80059	59965	3	60019	240100	200	160000	200	400000	80059	80057	1	1	80201	100	99	100	100	80000	80000	100	160014	14	36	0	0	160076	25	1	20	160062	16	0	0	0	0	0	0	5110	1	16	1	1	80044	80000	160000	80100	80190	80053	80060	80048	80048
160204	80047	621	1	0	1	1	0	0	0	21	0	0	0	1	80043	16	16	4	25	240100	80100	160000	80100	160000	1160734	3679908	0	80022	0	80183	80052	59973	3	60010	240100	200	160000	200	400000	80052	80053	1	1	80201	100	99	100	100	80000	80000	100	160014	14	38	0	1	160016	0	0	18	160002	16	34	14	0	0	0	1	5110	1	16	1	1	80057	80000	160000	80100	80061	80053	80048	80052	80192

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	80042	620	0	0	0	0	0	0	9	0	80027	16	16	0	25	240010	80010	160000	80010	160000	1879765	3679424	0	80015	80049	80042	59977	3	60022	240010	20	160000	20	400000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	36	0	0	160002	0	0	0	160002	2	0	0	0	5020	37	16	38	23	80039	80000	160000	80010	80050	80043	80043	80051	80043
160024	80040	620	0	0	0	0	0	0	6	0	80027	16	16	0	25	240010	80010	160000	80010	160000	1879765	3679424	0	80017	80042	80040	59977	3	60029	240010	20	160000	20	400000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	0	160000	2	38	0	0	5020	41	16	41	39	80039	80000	160000	80010	80043	80043	80050	80043	80051
160024	80042	621	0	0	0	0	0	0	3	0	80025	16	16	0	25	240010	80010	160000	80010	160000	1879765	3679424	0	80025	80042	80040	59977	3	60023	240010	20	160000	20	400000	80050	80051	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	5	160002	2	34	0	0	5020	38	16	38	38	80039	80000	160000	80010	80041	80041	80043	80043	80041
160024	80051	620	0	0	0	0	0	30	6	0	80027	16	16	0	25	240010	80010	160000	80010	160000	1879765	3679424	0	80259	80051	80040	59975	3	60020	240010	20	160120	20	400000	80320	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	2	160002	0	0	5	160002	2	34	0	0	5020	41	16	15	41	80048	80000	160000	80010	80043	80043	80115	80043	80043
160024	80042	620	0	0	0	0	0	21	9	0	80035	16	16	0	25	240010	80010	160000	80010	160000	1879765	3679424	0	80017	80051	80050	59977	3	60022	240010	20	160000	20	400000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	90	0	160002	4	0	5	160002	2	34	0	0	5020	37	16	42	42	80037	80000	160000	80010	80043	80043	80043	80044	80051
160024	80050	621	0	0	0	0	0	6	3	0	80027	16	16	0	25	240010	80010	160000	80010	160000	1320273	3682604	0	80017	80042	80042	59985	3	60022	240010	20	160000	20	400000	80040	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	2	0	5	160002	2	34	0	0	5020	42	16	40	37	80039	80000	160000	80010	80051	80043	80043	80043	80043
160024	80050	620	0	0	0	0	0	0	9	0	80027	16	16	0	25	240010	80010	160000	80010	160000	1879765	3679424	0	80017	80050	80051	59977	3	60022	240010	20	160000	20	400000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	5	160002	2	34	0	0	5020	43	16	38	36	80039	80000	160000	80010	80051	80043	80147	80041	80041
160024	80042	620	0	0	0	0	0	0	3	0	80027	16	0	0	25	240010	80010	160000	80010	160000	1320265	3679808	0	80024	80042	80042	59977	3	60020	240010	20	160000	20	400000	80049	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160000	0	0	0	160002	2	34	0	0	5020	39	16	37	40	80039	80000	160000	80010	80051	80043	80043	80041	80043
160024	80042	620	0	0	0	0	0	0	3	0	80027	16	16	0	25	240010	80010	160000	80010	160000	1879765	3679424	0	80017	80050	80050	59977	3	60029	240010	20	160000	20	400000	80042	80040	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	2	160002	2	34	0	0	5020	44	16	43	43	80039	80000	160000	80010	80051	80043	80043	80050	80041
160024	80042	620	0	0	0	0	0	0	6	0	80027	16	16	0	25	240010	80010	160000	80010	160000	1879765	3679424	0	80017	80050	80051	59977	3	60020	240010	20	160000	20	400000	80040	80040	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	7	0	8	160002	0	34	0	0	5020	42	16	38	37	80039	80000	160000	80010	80053	80051	80041	80049	80043

ST1 (multiple, post-index, 2 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations