Firestorm: ST1 (multiple, post-index, 3 regs, 16B) measurements

Code:

  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5e	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
63005	28787	233	0	0	2	0	0	1	0	0	0	0	3	1	0	0	4742	28743	0	0	22789	4000	1000	3000	1000	3000	5000	15903	0	8	0	7	17034	28268	28835	3	10	4000	3000	7000	28760	28856	1	1	61001	1000	1000	3000	0	9	0	3001	0	0	0	3000	0	6	0	0	0	13249	9547	6924	3135	0	84	20295	3143	3828	17	66	59	2	28311	1000	15487	12619	13954	3000	1000	28728	29002	28825	28917	28681
63004	28894	232	0	0	1	0	0	1	0	0	0	6	1	0	0	0	4784	28724	0	0	22614	4000	1000	3000	1000	3000	5000	15904	0	2	0	8	17031	28136	29024	3	10	4000	3000	7000	28833	28833	1	1	61001	1000	1000	3000	0	0	0	3000	0	0	0	3000	0	0	0	0	0	13215	9453	6935	3147	0	80	20083	3165	3825	19	62	59	3	28285	1000	15667	12597	13687	3000	1000	28937	28991	28885	28795	28882
63004	28913	232	1	0	1	0	0	0	0	0	0	6	1	0	0	0	4687	28677	3	0	22907	4000	1000	3000	1000	3000	5000	15912	0	7	0	0	17023	28312	28982	3	10	4000	3000	7000	28788	28697	1	1	61001	1000	1000	3000	0	9	0	3000	1	0	0	3000	0	9	0	0	0	13033	9401	6950	3169	1	68	20252	3280	3822	21	61	59	3	28338	1000	15546	12662	13914	3000	1000	28909	28886	28831	28766	28961
63004	28818	231	0	0	0	0	0	0	0	0	0	0	0	0	0	0	4619	28707	4	0	22612	4000	1000	3000	1000	3000	5000	15907	0	10	1	8	17026	28342	28834	3	10	4000	3000	7000	28839	28775	1	1	61001	1000	1000	3000	0	9	0	3000	7	0	3	3000	0	0	0	0	0	13182	9429	7008	3149	0	68	20150	3247	3825	15	59	56	3	28172	1000	15748	12774	13862	3000	1000	28766	28777	28762	28694	29154
63004	28964	231	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4694	28560	4	4	22767	4000	1000	3000	1000	3000	5000	15903	0	0	0	9	17040	28248	28725	3	10	4000	3000	7000	28830	28709	1	1	61001	1000	1000	3000	0	0	0	3001	0	0	0	3000	0	9	0	0	0	13102	9353	6966	3148	0	77	20228	3239	3828	26	51	51	2	28208	1000	15691	12397	13679	3000	1000	28916	28865	28885	28884	28737
63004	28979	232	0	0	0	0	0	1	0	0	0	3	1	0	0	0	4742	28610	2	4	22703	4000	1000	3000	1000	3000	5000	15902	0	9	0	0	17045	28155	28903	3	10	4000	3000	7000	28853	28790	1	1	61001	1000	1000	3000	0	0	0	3000	0	0	0	3000	0	9	0	0	0	13354	9558	6937	3185	1	75	20308	3286	3826	30	54	53	2	28195	1000	15705	12685	13955	3000	1000	28850	28787	28796	28973	28920
63004	29091	232	0	0	1	0	0	0	0	0	0	0	0	0	0	0	4768	28656	3	0	22771	4000	1000	3000	1000	3000	5000	15902	0	9	0	0	17034	28251	28916	3	10	4000	3000	7000	28796	28775	1	1	61001	1000	1000	3000	0	9	0	3000	1	0	0	3000	0	9	0	0	0	13270	9432	6990	3218	0	77	20115	3246	3823	20	51	55	3	28231	1000	15288	12625	14060	3000	1000	28862	28844	28828	28789	28940
63004	28919	232	0	0	0	0	0	0	0	0	0	12	0	0	0	0	4658	29286	0	0	22736	4000	1000	3000	1000	3000	5000	15906	0	8	1	0	17054	28261	28967	3	10	4000	3000	7000	28807	28906	1	1	61001	1000	1000	3000	0	9	0	3000	0	0	0	3000	0	9	0	0	0	13153	9411	6950	3192	1	62	20245	3237	3823	24	55	46	2	28239	1000	15717	12833	13676	3000	1000	28784	28866	28739	29012	28915
63004	28886	232	0	0	1	0	0	1	0	0	0	0	3	0	0	0	4687	28721	0	0	22810	4000	1000	3000	1000	3000	5000	15905	0	5	0	8	17035	28188	28856	3	10	4000	3000	7000	28834	28781	1	1	61001	1000	1000	3000	0	0	0	3000	0	0	0	3000	0	0	0	0	0	13239	9220	6940	3207	0	68	20269	3156	3824	20	63	58	3	28291	1000	15650	12515	13855	3000	1000	28835	28956	28797	28909	28834
63004	28839	233	1	0	0	0	0	1	0	0	0	0	1	0	0	0	4778	28740	0	0	22708	4000	1000	3000	1000	3000	5000	15902	0	9	1	0	17037	28290	28829	3	10	4000	3000	7000	28832	28840	1	1	61001	1000	1000	3000	0	9	0	3000	0	0	0	3000	0	0	0	0	0	13142	9167	6905	3123	2	70	20180	3245	3820	24	59	64	2	28232	1000	15804	12732	13948	3000	1000	28802	28849	28963	28924	28787

Count: 8

Code:

  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	18	19	1e	1f	22	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	120051	930	0	0	0	0	0	0	0	9	0	0	120036	16	16	0	25	320100	80100	240000	80100	240000	470715	5519424	0	120017	0	120040	120123	89955	3	90007	320100	200	240000	200	560000	120052	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	1	0	5	240002	2	34	0	0	0	0	5110	1	16	1	1	120039	80000	240000	80100	120043	120052	120043	120043	120051
240204	120049	930	0	0	0	0	0	0	0	3	0	0	120027	16	16	0	25	320100	80100	240000	80100	240000	470715	5519352	1	120017	0	120042	120042	89955	3	90000	320100	200	240000	200	560000	120042	120040	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240000	1	0	11	240002	2	34	0	0	0	0	5110	1	16	2	1	120039	80000	240000	80100	120043	120043	120043	120052	120051
240204	120050	931	0	0	0	0	0	0	0	9	0	0	120027	16	16	0	25	320100	80153	240000	80100	240000	470713	5519424	0	120017	0	120042	120042	89955	3	90000	320100	200	240000	200	560000	120042	120050	1	1	80201	100	99	100	100	80000	80000	100	240000	0	38	0	0	240002	0	0	5	240002	2	34	0	0	0	0	5110	1	16	1	1	120047	80000	240000	80100	120041	120041	120053	120043	120043
240204	120042	964	0	0	0	0	0	0	39	3	0	0	120027	16	16	0	25	320100	80100	242820	80100	240000	470715	5519760	0	120026	0	120042	120054	89955	3	90110	320100	200	240000	200	560000	120042	120040	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	1	0	2	240002	2	36	0	0	0	0	5110	1	16	1	1	120039	80000	240000	80100	120041	120043	120043	120051	120041
240204	120050	930	0	0	0	0	0	0	18	3	0	0	120027	16	16	0	25	320100	80100	240000	80160	240000	470713	5519424	0	120015	0	120050	120042	89955	3	90110	320100	200	240000	200	560000	120042	120049	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	8	240002	2	34	0	0	0	0	5110	1	26	1	1	120048	80000	240000	80100	120041	120043	120181	120043	120043
240204	120042	931	0	0	0	0	0	0	12	9	0	0	120027	16	16	0	25	320100	80100	240000	80100	240108	470713	5519424	0	120017	0	120042	120042	89955	3	90000	320100	200	240000	200	560000	120042	120053	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	1	0	2	240002	2	0	0	0	0	0	5110	1	16	1	1	120113	80000	240000	80100	120043	120043	120043	120050	120051
240204	120040	964	0	0	0	0	0	1	3	3	0	0	120027	16	16	0	25	320100	80100	240000	80100	240000	470715	5519808	0	120024	0	120050	120042	89955	3	90000	320100	200	240000	200	560000	120042	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	5	240002	2	34	0	0	0	0	5110	1	16	1	1	120039	80000	240000	80100	120052	120043	120044	120052	120043
240204	120042	964	0	0	0	0	0	4	78	3	0	0	120033	0	16	0	25	320100	80100	240000	80100	240000	470710	5541384	0	120015	0	120042	120052	89963	3	90000	320100	200	240000	200	560000	120171	120040	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	14	240002	2	34	0	0	0	0	5136	1	35	1	1	120039	80000	240000	80100	120044	120043	120052	120043	120043
240204	120042	949	0	0	0	0	0	0	0	3	0	0	120027	16	16	0	25	320100	80100	240000	80100	240000	470715	5519784	0	120031	0	120178	120043	90143	9	90001	320100	202	240360	1063	560000	120177	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	4	0	240002	1	0	3162	240000	2	34	4	1	0	0	5110	3	16	1	1	120039	80000	240000	80100	120041	120052	120043	120043	120043
240204	120042	930	0	0	0	0	0	0	12	3	0	0	120035	16	16	0	25	320100	80100	240000	80100	240000	470664	5519424	0	120017	0	120050	120042	89955	3	90000	320260	200	240000	200	560000	120040	120040	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	2	2	240002	0	34	0	0	0	0	5110	1	16	1	1	120037	80000	240000	80100	120043	120051	120043	120043	120043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d2	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	120052	930	1	1	0	1	0	0	0	19	0	0	0	1	120037	16	16	5	25	320010	80010	240000	80010	240000	470147	5520220	120027	0	120052	120058	89995	3	90039	320010	20	240000	20	560000	120051	120058	1	1	80021	10	9	10	10	80000	80000	10	240015	14	38	0	0	240016	0	1	17	240002	16	34	14	0	5020	0	5	16	1	4	3	120048	80000	240000	80010	120059	120054	120062	120048	120059
240024	120061	930	1	0	0	1	0	0	0	17	0	0	0	1	120038	16	16	6	25	320010	80010	240000	80010	240000	470141	5519692	120025	0	120050	120052	89993	3	90037	320010	20	240000	20	560000	120052	120059	1	1	80021	10	9	10	10	80000	80000	10	240014	14	36	0	0	240016	0	0	20	240062	16	36	14	1	5020	0	4	53	3	3	3	120543	80000	240000	80010	120053	120444	120601	120052	122579
240024	120053	964	1	0	0	1	0	0	15	19	0	1	0	1	120036	16	16	2	25	320010	80010	240000	80010	240000	470147	5520174	120027	0	120051	120058	89994	3	90040	320301	20	240000	20	560000	120050	120060	1	1	80021	10	9	10	10	80000	80000	10	240014	14	35	2	0	240016	0	0	20	240002	16	0	14	0	5020	0	5	16	0	3	4	120049	80000	240000	80010	120060	120054	120061	120059	120060
240024	120059	930	1	0	0	1	0	0	183	19	0	0	0	1	120043	16	16	7	25	320010	80010	240000	80010	240000	470139	5520268	121825	0	120052	120448	90342	12	90405	320155	20	245405	20	564195	122067	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	29	0	240065	0	0	8	240002	2	42	0	0	5020	0	8	16	0	4	4	120049	80000	240000	80010	120044	120043	120043	120043	120043
240024	120042	899	0	0	0	0	0	0	0	3	0	0	0	0	120027	16	16	1	25	320010	80010	240000	80010	240000	470195	5519472	120017	0	120042	120042	89977	3	90022	320010	20	240000	20	560000	120046	120063	1	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	0	240016	1	0	260	240002	16	34	0	0	5020	0	4	16	0	5	4	120047	80000	240000	80010	120043	120043	120050	120043	120043
240024	120042	899	0	0	0	0	0	0	0	14	0	0	1	0	120027	16	0	0	25	320010	80010	240000	80010	240000	470198	5519424	120017	0	120042	120042	89982	3	90022	320010	20	240000	20	560000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	2	240002	2	34	0	0	5020	0	3	16	0	3	3	120056	80000	240000	80010	120050	120043	120043	120050	120043
240024	120042	899	0	0	0	0	0	0	0	9	0	0	0	0	120027	16	0	0	25	320010	80010	240000	80010	240000	470198	5519352	120017	0	120052	120042	89982	3	90020	320010	20	240000	20	560000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	2	240002	0	34	14	0	5020	0	4	16	0	5	5	120057	80000	240000	80010	120043	120043	120052	120435	120827
240024	120049	930	0	0	0	0	0	0	0	3	0	0	0	0	120572	16	16	0	25	320010	80010	240000	80010	240000	470198	5519352	120017	0	120047	120042	89985	3	90022	320010	20	240000	20	560000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	36	0	0	240002	8	0	5	240002	2	34	14	0	5020	0	2	16	0	4	3	120342	80000	240000	80010	120043	120062	120043	120043	120049
240024	120042	930	1	0	0	0	0	0	0	3	0	0	0	0	120035	16	16	0	25	320010	80010	240000	80010	240000	470147	5519424	120017	0	120042	120049	89985	3	90022	320010	20	240000	20	560000	120042	120057	1	1	80021	10	9	10	10	80000	80000	10	240000	0	36	0	0	240002	0	0	2	240002	2	34	0	0	5020	0	2	16	0	3	5	120039	80000	240000	80010	120051	120059	120043	120173	120043
240024	120052	931	1	0	0	0	0	0	0	3	0	0	0	1	120027	16	16	0	25	320010	80047	240000	80010	240000	470147	5519808	120024	0	120042	120042	89977	3	90022	320010	20	240000	20	560000	120050	120052	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	1	0	2	240002	2	34	0	0	5020	0	5	16	0	3	5	120047	80000	240000	80010	120043	120174	120043	120043	120043

ST1 (multiple, post-index, 3 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations