Firestorm: ST1 (multiple, post-index, 3 regs, 2D) measurements

Code:

  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	l1d cache miss st nonspec (c0)	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29833	236	25	1	37	1	10	12	924	616	0	0	1	4552	30133	0	23698	4036	1005	3021	1010	3021	5025	16647	3	0	6	17278	29547	30168	3	10	4000	3000	7000	29342	29305	1	1	61001	1000	1000	3000	6	3000	1	0	46	6	3000	0	0	13089	9397	6869	3157	9	73	20819	3321	3817	11	74	70	28561	1000	16175	13151	13977	3000	1000	29392	29501	29423	29388	29385
63004	29344	228	33	0	27	0	0	0	0	0	0	0	1	4656	29237	0	23989	4000	1000	3000	1000	3000	5000	15904	3	0	9	17035	28531	29542	3	10	4000	3000	7000	29270	29299	1	1	61001	1000	1000	3000	0	3000	8	0	0	3	3000	0	0	13165	9529	6895	3192	14	61	20916	3323	3813	13	74	72	28756	1000	15945	13243	14493	3000	1000	29406	29381	29493	29517	29548
63004	29401	229	28	0	25	0	0	0	0	1	0	0	0	4710	29239	0	23449	4000	1000	3000	1000	3000	5000	15905	2	0	0	17047	28634	29558	3	10	4000	3000	7000	29402	29448	1	1	61001	1000	1000	3000	6	3000	34	0	0	3	3000	0	0	13111	9256	6933	3155	15	66	20642	3238	3808	14	80	62	28571	1000	16362	13207	14446	3000	1000	29413	29589	29491	29410	29404
63004	29602	228	28	0	25	0	0	0	0	1	0	0	0	4689	29315	0	23512	4000	1000	3000	1000	3003	5000	15904	4	0	0	17036	28691	29564	3	10	4000	3000	7000	29410	29356	1	1	61001	1000	1000	3000	6	3000	33	0	0	0	3000	6	0	13284	9357	6940	3128	13	62	20877	3282	3810	20	75	71	28811	1000	16307	13162	14361	3000	1000	29616	29559	29602	29640	29616
63004	29475	237	28	0	25	0	0	0	0	1	0	0	0	4675	29708	0	23479	4000	1000	3000	1000	3003	5000	15910	1	0	0	17027	28843	29582	3	10	4004	3003	7000	29337	29509	1	1	61001	1000	1000	3000	6	3001	53	2	0	1680	3000	9	0	13184	9299	6969	3129	15	68	20710	3314	3814	21	68	67	28731	1000	16295	13017	14549	3000	1000	29434	29647	29627	29479	28764
63004	28903	235	29	0	24	0	0	0	9	1	0	0	0	4770	28205	0	22722	4000	1000	3000	1001	3000	5000	15909	6	0	0	17039	28102	28850	3	10	4000	3003	7000	28564	28684	1	1	61001	1000	1000	3000	6	3000	39	0	0	0	3000	6	0	13289	9465	6996	3174	12	66	20175	3182	3809	28	67	70	28375	1000	15463	12485	13906	3000	1000	28774	28808	28842	28902	28856
63004	28729	223	25	0	33	0	0	0	0	1	0	0	0	4724	28616	0	22559	4000	1000	3000	1000	3000	5000	15900	6	1	0	17062	28172	28788	8	10	4000	3000	7000	28588	28596	1	1	61001	1000	1000	3000	6	3000	6	0	0	407	3000	0	0	13356	9417	6955	3123	16	70	20159	3188	3812	23	69	74	28162	1000	15719	12396	13909	3000	1000	28785	29187	28887	28951	28811
63004	28745	223	26	0	26	0	0	0	0	1	0	0	0	4745	28644	0	22745	4000	1000	3000	1000	3000	5000	15897	5	1	0	17040	28183	28798	3	10	4000	3000	7000	28756	28668	1	1	61001	1000	1000	3000	6	3000	5	0	0	9	3000	6	0	13326	9538	6854	3109	11	70	20244	3208	3814	30	70	77	28252	1000	15615	12603	13999	3000	1000	28789	28901	28794	28835	28885
63004	28861	223	30	0	25	0	0	0	0	1	0	0	0	4773	28776	2	22736	4000	1001	3000	1000	3000	5000	15897	8	0	0	17074	28188	28834	3	10	4000	3000	7000	28721	28706	1	1	61001	1000	1000	3004	6	3000	4	2	0	9	3000	6	0	13075	9312	6934	3156	16	69	20239	3166	3809	28	66	74	28255	1000	15750	12467	14052	3000	1000	28822	28889	28879	28963	28963
63004	28856	223	28	0	27	0	0	0	0	0	0	0	0	4654	28649	0	22762	4000	1000	3000	1000	3000	5000	15903	4	1	0	17038	28175	28877	3	10	4000	3000	7000	28651	28685	1	1	61001	1000	1000	3000	6	3000	57	2	0	3	3000	0	0	13225	9456	6934	3090	16	70	20159	3200	3815	34	75	71	28244	1001	15688	12510	13983	3000	1000	28848	28992	28729	28924	28830

Count: 8

Code:

  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	120042	930	0	0	0	0	0	0	12	3	0	0	1	120027	16	16	1	25	320100	80100	240000	80100	240000	470712	5519448	120017	120042	120040	89955	3	90001	320100	200	240000	200	560000	120042	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	0	0	0	240002	1	0	2	240002	2	42	0	0	0	0	5112	5	16	5	6	120037	80000	240000	80100	120043	120044	120043	120043	120043
240204	120042	930	0	0	0	0	0	0	132	3	0	0	1	120027	16	16	0	25	320209	80100	240000	80100	240000	470712	5519448	120029	120042	120042	89955	3	90000	320100	200	240000	200	560000	120042	120042	2	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240016	0	0	21	240002	2	42	0	0	0	0	5130	5	16	5	5	120048	80000	240000	80100	120043	120044	120055	120043	120041
240204	120042	931	1	0	0	1	0	0	144	20	0	0	2	120039	16	16	2	48	320100	80100	240000	80100	240000	470658	5519448	120015	120042	120042	89953	3	90000	320100	200	240000	200	560000	120040	120180	1	1	80201	100	99	100	100	80000	80000	100	240015	14	50	0	0	240016	0	1	20	240002	2	42	0	0	0	0	5112	5	16	4	5	120039	80057	240000	80100	120044	120043	120043	120041	120044
240204	120040	931	1	0	0	0	0	0	0	3	1	0	1	120027	16	0	1	25	320100	80100	240000	80100	240000	470712	5519976	120017	120042	120042	90242	37	90548	320835	200	240600	202	561667	120726	120722	6	1	80201	100	99	100	100	80000	80000	100	240180	0	42	0	0	240002	0	0	2047	240002	2	42	0	0	0	0	5112	5	44	6	3	120659	80200	240000	80100	120723	120780	120831	120722	120047
240204	120040	931	0	0	0	0	1	0	0	3	0	0	1	120029	16	16	1	25	320100	80100	240000	80100	240108	470712	5519448	120017	120043	120042	90405	3	89998	320100	200	240000	200	560000	120042	120043	1	1	80201	100	99	100	100	80000	80000	100	240060	0	42	0	0	240002	1	0	2	240002	2	42	0	0	0	0	5112	3	16	5	5	120039	80000	240000	80100	120043	120041	120043	120043	120043
240204	120042	930	0	0	0	0	0	0	0	3	0	0	1	120027	16	16	1	25	320100	80137	240000	80100	240000	470712	5519448	120015	120042	120042	89955	3	89998	320100	200	240000	200	560000	120042	120040	1	1	80201	100	99	100	100	80000	80000	100	240015	14	44	0	1	240016	1	1	786	240002	2	42	0	0	0	0	5112	5	16	5	5	120040	80000	240000	80100	120043	120043	120045	120043	120043
240204	120042	930	0	0	0	0	1	0	3	0	1	0	1	120027	16	16	4	50	320100	80100	240000	80102	240000	470712	5519904	125367	120044	120043	89955	3	90000	320100	200	240000	200	560000	120042	120043	1	1	80201	100	99	100	100	80000	80000	100	240014	14	44	0	0	240016	1	2	794	240004	2	42	0	0	0	0	5112	5	16	4	5	120039	80000	240000	80100	120043	120043	120044	120043	120044
240204	120043	931	1	0	0	0	0	0	0	3	0	0	1	120027	16	0	0	25	320197	80100	240000	80100	240000	470720	5519448	120017	120042	120042	89956	3	89998	320100	200	240000	200	560000	120180	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	42	32	0	240000	1	0	5	240002	2	42	0	0	0	0	5112	3	16	5	5	120040	80000	240000	80100	120043	120041	120043	120043	120043
240204	120042	930	0	0	0	0	0	0	0	3	0	0	1	120027	16	0	1	25	320100	80100	240000	80100	240000	470712	5519448	120017	120043	120042	89953	3	90000	320258	200	240000	200	560000	120042	120054	1	1	80201	100	99	100	100	80000	80000	100	240000	0	0	0	0	240002	0	0	3	240000	2	44	0	0	0	0	5112	5	16	6	5	120039	80000	240000	80100	120043	120045	120043	120043	120044
240204	120042	931	0	0	0	0	0	0	12	0	0	1	1	120027	16	16	0	25	320100	80100	240000	80100	240000	472122	5519692	120030	120192	120052	89966	3	90012	320100	200	240121	200	560000	120063	120052	1	1	80201	100	99	100	100	80000	80000	100	240015	14	44	0	0	240014	0	1	16	240002	2	42	0	0	0	0	5112	3	16	5	3	120040	80000	240000	80100	120041	120043	120044	120043	120043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	120043	930	0	1	0	0	0	3	0	0	120027	16	16	75	25	320010	80010	240000	80010	240000	470195	5519616	0	120015	0	120040	120043	90070	3	90033	320010	20	240000	20	560000	120175	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	32	240002	1	0	2	240002	2	42	0	5020	12	26	12	12	120039	80000	240000	80010	120043	120043	120041	120176	120041
240024	120042	930	0	0	0	0	21	3	0	0	120025	16	16	0	25	320010	80010	240000	80010	240000	470195	5519448	0	120017	0	120172	120042	89977	3	90024	320010	20	240121	20	560000	120040	120040	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	240002	1	0	8	240002	2	42	0	5033	12	16	7	13	120039	80000	240000	80010	120055	120043	120043	120041	120041
240024	120042	932	1	0	0	0	0	3	0	0	120027	16	16	1	25	320010	80010	240060	80010	240000	470203	5519448	0	120017	0	120042	120042	89977	3	90131	320010	20	240000	20	560000	120042	120040	1	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	240002	1	0	2	240002	0	42	0	5020	7	16	13	7	120051	80039	240000	80010	120043	120043	120043	120043	120043
240024	120184	931	0	0	0	0	0	3	0	0	120039	16	16	0	25	320010	80010	240000	80010	240000	470195	5519496	0	120015	0	120173	120042	89977	3	90022	320010	20	240119	20	560000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	240002	0	0	2	240062	0	42	0	5034	12	16	12	12	120040	80000	240000	80010	120044	120044	120043	120043	120043
240024	120043	931	0	0	0	0	0	3	0	0	120025	16	16	6	25	320010	80010	240000	80047	240000	470195	5519472	0	120018	0	120040	120043	89975	3	90022	320010	20	240000	20	560000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	240002	0	0	5	240002	2	42	0	5020	5	16	12	13	120039	80000	240000	80010	120043	120043	120043	120044	120043
240024	120043	930	0	0	0	0	0	3	0	0	120027	16	16	6	25	320010	80010	240000	80010	240000	470195	5519472	0	120018	0	120042	120175	89987	3	90022	320010	20	240000	20	560000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	240002	0	0	5	240062	2	46	0	5020	5	16	5	12	120160	80000	240000	80010	120044	120044	120043	120044	120119
240024	120042	931	0	0	0	0	0	3	0	0	120028	16	16	0	25	320010	80010	240000	80010	240000	470195	5519472	0	120015	0	120042	120042	89977	3	90020	320010	20	240000	20	560000	120043	120042	2	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	240002	0	0	2	240000	2	42	0	5020	5	16	13	13	120039	80000	240000	80010	120043	120041	120179	120043	120041
240024	120042	931	0	0	1	0	0	3	0	0	120028	16	16	1	25	320010	80010	240000	80010	240000	470195	5524356	0	120015	0	120042	120040	89975	3	90020	320010	20	240000	20	560000	120046	120044	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	240002	1	0	750	240002	2	0	0	5020	7	16	13	5	120039	80000	240000	80010	120043	120044	120044	120044	120088
240024	120042	931	0	0	0	0	0	3	0	0	120027	16	16	74	50	320010	80048	240120	80010	242808	470920	5533836	0	120381	0	120314	120440	90255	25	90129	320301	20	240119	20	560557	120304	120313	4	1	80021	10	9	10	10	80000	80000	10	240127	0	42	32	240122	0	0	2307	240122	2	42	2	5033	12	35	17	14	123057	80112	240000	80010	120180	120439	120309	120316	120307
240024	120178	935	0	1	3	1	132	179	0	0	120025	16	16	1	25	320010	80010	240000	80010	240000	470195	5519976	0	120018	0	120042	120043	89977	3	90022	320010	20	240000	20	560000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	240002	1	0	5	240002	2	0	0	5020	11	16	5	12	120039	80000	240000	80010	120043	120043	120041	120043	120043

ST1 (multiple, post-index, 3 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations