Firestorm: ST1 (multiple, post-index, 3 regs, 4S) measurements

Code:

  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29100	232	4	1	4	0	1	2	1	0	0	0	4	0	0	0	4694	28856	0	0	23002	4000	1000	3000	1000	3000	5000	15907	16	0	0	17018	0	28414	29077	3	10	4000	3003	7000	28722	28714	1	1	61001	1000	1000	3009	6	9	3	3003	1	9	3	3000	3	9	3	8	0	13192	9223	7018	3140	0	61	20167	3227	3816	23	52	55	28349	1000	15667	12437	13885	3000	1000	28731	28828	28941	28808	28727
63004	28781	231	0	1	1	0	0	0	2	0	3	0	4	1	0	0	4519	28603	0	0	22789	4017	1005	3012	1003	3012	5020	16056	14	0	0	17026	0	28279	28772	8	10	4000	3006	7014	28967	28980	4	1	61001	1000	1000	3012	6	9	0	3000	1	0	943	3003	3	6	3	3	0	13003	9161	6813	3147	0	53	20394	3272	3821	27	56	60	28439	1002	15690	12794	14523	3000	1000	29020	29199	29176	29296	29089
63004	28965	233	0	1	0	2	2	0	2	0	0	18	4	0	0	0	4651	28817	0	0	23105	4000	1000	3000	1000	3000	5000	15908	4	0	8	17028	0	28648	29145	3	10	4000	3000	7000	29001	29228	3	1	61001	1000	1000	3004	4	6	1	3003	0	1	6	3000	3	6	3	1	0	13337	9371	6881	3186	0	62	20456	3108	3821	20	54	55	28413	1000	15488	12638	13809	3000	1000	28883	29064	28993	29113	28967
63004	28899	233	0	1	2	1	0	0	1	0	0	0	4	0	0	0	4719	28805	0	0	22990	4000	1000	3000	1000	3000	5000	15910	12	0	9	17045	0	28274	28880	3	10	4000	3000	7000	28890	28778	1	1	61001	1000	1000	3004	4	6	0	3003	0	0	3	3000	3	6	3	3	223	13073	9162	6858	3191	0	58	20494	3091	3812	55	53	56	28676	1007	15613	12619	14091	3000	1000	29399	29495	29244	29171	29491
63004	29320	236	2	1	0	0	0	0	0	7	7	924	444	0	0	0	4700	29036	0	0	22971	4020	1006	3015	1008	3033	5045	16711	2	0	0	17603	0	28785	29422	72	340	4044	3000	7000	28861	28923	1	1	61001	1000	1000	3003	3	6	2	3003	1	1	3	3000	3	6	3	2	0	13066	9355	7012	3190	1	56	20089	3218	3830	21	55	62	28244	1000	15533	12722	13856	3000	1000	28796	28830	28855	28707	28765
63004	28844	233	4	1	0	0	1	2	0	0	0	93	4	0	0	1	4870	28561	0	0	22600	4000	1000	3000	1000	3000	5000	15908	7	1	0	17059	0	28287	28776	3	10	4000	3000	7000	28513	28595	1	1	61001	1000	1000	3004	5	6	1	3003	0	0	3	3000	0	6	3	1	0	13286	9435	7069	3262	1	62	20080	3133	3822	30	56	58	28127	1000	15487	12703	13386	3000	1000	28735	28654	28689	28646	28719
63004	28822	223	0	1	0	0	0	1	1	0	0	0	4	0	0	1	4854	28547	0	0	22690	4000	1000	3000	1000	3000	5000	15899	8	0	8	17043	0	28092	28706	3	10	4000	3000	7000	28734	28576	1	1	61001	1000	1000	3005	5	0	0	3003	0	1	3	3000	3	6	3	1	0	13185	9309	6975	3196	0	51	20070	3165	3820	24	59	60	28207	1000	15342	12373	13557	3000	1000	28547	28749	28669	28721	28709
63004	28824	224	1	1	1	1	1	1	1	0	0	0	3	0	0	0	4722	28531	0	0	22655	4000	1000	3000	1000	3000	5000	15909	12	0	0	17057	0	28116	28734	3	10	4000	3000	7000	28736	28595	1	1	61001	1000	1000	3004	4	6	1	3003	0	1	3	3000	3	0	3	0	0	12903	9397	6931	3122	0	61	20151	3153	3821	26	54	59	28200	1000	15343	12603	13741	3000	1000	28685	28713	28787	28747	28729
63004	28705	223	0	1	1	1	1	0	0	0	0	12	4	0	0	1	4708	28767	1	0	22681	4000	1000	3000	1000	3000	5000	15900	6	1	0	17041	0	28245	28954	3	10	4004	3000	7000	28936	28787	1	1	61001	1000	1000	3003	3	6	1	3003	0	0	3	3000	3	0	3	1	0	13217	9399	6890	3201	0	56	20196	3142	3809	31	56	54	28230	1000	15454	12274	14124	3000	1000	28850	28976	28829	28925	28760
63004	28964	224	0	1	1	1	1	1	1	0	0	0	4	0	0	0	4680	28782	3	0	22788	4000	1000	3000	1000	3000	5000	15907	0	0	9	17029	0	28272	28870	3	10	4000	3000	7000	28881	28687	1	1	61001	1000	1000	3004	5	0	2	3003	0	1	3	3000	3	6	3	1	0	13115	9299	6967	3198	0	64	20220	3201	3813	17	58	59	28172	1000	15482	12430	13784	3000	1000	28813	28958	28798	28798	28977

Count: 8

Code:

  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	120053	930	1	0	0	0	0	0	0	0	14	0	0	0	1	120045	16	14	80	81	320200	80151	240000	80185	240216	471026	5525200	0	0	0	120269	120326	120328	90251	18	90245	320408	200	240119	200	560560	120461	120319	3	1	80201	100	99	0	100	100	80000	80000	100	240014	17	36	0	0	240076	0	0	800	240002	2	34	0	0	0	5147	0	0	14	215	8	4	120175	80037	240000	80100	120317	120444	120325	120463	120176
240204	120440	931	1	1	1	1	0	2	2	264	267	0	0	0	1	120032	16	16	5	25	320100	80100	240000	80100	240000	470662	5519908	0	0	0	120022	120047	120047	89972	3	90005	320100	200	240000	200	560000	120059	120053	1	1	80201	100	99	0	100	100	80000	80000	100	240015	15	42	0	1	240016	0	0	14	240002	16	35	14	1	0	5110	0	0	3	16	2	3	120039	80000	240000	80100	120059	120041	120051	120043	120043
240204	120061	964	0	0	0	0	1	0	0	0	6	0	0	0	0	120025	16	16	0	25	320100	80100	240000	80100	240000	470715	5520048	0	0	0	120017	120059	120050	89955	3	90000	320100	200	240000	200	560000	120058	120052	1	1	80201	100	99	0	100	100	80000	80000	100	240015	14	0	0	1	240014	0	0	16	240002	2	34	14	0	0	5110	0	0	3	16	2	3	120039	80000	240000	80100	120052	120041	120043	120052	120050
240204	120042	964	0	0	0	0	0	0	0	30	3	0	0	0	1	120027	16	16	0	25	320100	80100	240000	80100	240000	470710	5519424	0	0	0	120017	120042	120042	89955	3	90018	320100	200	240000	200	560000	120050	120059	1	1	80201	100	99	0	100	100	80000	80000	100	240014	15	36	0	1	240016	1	0	19	240002	0	34	0	0	0	5110	0	0	4	16	3	3	120039	80000	240000	80100	120051	120043	120043	120052	120051
240204	120042	964	0	0	0	0	0	0	0	0	3	0	0	0	1	120043	0	16	0	25	320100	80100	240000	80100	240000	470664	5520150	0	0	0	120033	120059	120063	89963	3	90005	320100	200	240000	200	560000	120062	120068	1	1	80201	100	99	0	100	100	80000	80000	100	240015	15	36	0	0	240016	0	0	19	240002	16	36	14	1	0	5110	0	0	3	16	4	2	120039	80000	240000	80100	120043	120043	120043	120043	120050
240204	120050	964	0	0	0	0	0	0	0	0	0	0	0	0	0	120027	16	16	0	25	320100	80100	240000	80100	240000	470715	5519856	0	0	0	120017	120042	120050	89955	3	90000	320100	200	240000	200	560000	120058	120050	1	1	80201	100	99	0	100	100	80000	80000	100	240014	14	0	0	0	240016	1	0	14	240002	16	0	14	1	0	5110	0	0	3	16	3	3	120048	80000	240000	80100	120060	120052	120059	120059	120060
240204	120047	964	1	0	0	1	0	0	0	12	15	0	0	0	0	120025	16	16	3	25	320100	80100	240000	80100	240000	470712	5519424	1	0	0	120017	120059	120048	89953	3	90000	320100	200	240000	200	560000	120054	120052	1	1	80201	100	99	0	100	100	80000	80000	100	240014	14	36	0	0	240016	0	0	20	240000	2	34	14	0	0	5110	0	0	3	16	2	3	120047	80000	240000	80100	120043	120043	120050	120043	120060
240204	120042	964	0	0	0	0	0	0	0	12	3	0	0	1	1	120027	15	16	0	25	320100	80100	240000	80100	240000	470715	5519424	0	0	0	120017	120042	120042	89962	3	90010	320100	200	240000	200	560000	120052	120047	1	1	80201	100	99	0	100	100	80000	80000	100	240014	15	36	0	1	240016	0	0	21	240000	2	34	0	0	0	5110	0	0	2	16	2	3	120039	80000	240000	80100	120043	120041	120041	120043	120043
240204	120042	964	0	0	0	0	0	0	0	0	18	0	0	0	0	120027	16	16	0	25	320100	80100	240000	80100	240000	470713	5519424	0	0	0	120026	120040	120042	89953	3	90000	320100	200	240000	200	560000	120060	120052	1	1	80201	100	99	0	100	100	80000	80000	100	240014	14	36	0	0	240016	1	1	17	240002	16	36	14	0	0	5110	0	0	3	16	3	2	120050	80000	240000	80100	120060	120060	120052	120048	120060
240204	120060	965	1	0	0	0	0	0	0	0	21	0	0	0	0	120027	16	0	0	25	320100	80100	240000	80100	240000	470664	5519424	0	0	0	120017	120042	120042	89973	16	90217	320392	200	240239	200	560842	120456	120314	4	1	80201	100	99	0	100	100	80000	80000	100	240197	14	34	59	0	240196	0	0	1577	240180	2	52	0	0	0	5151	0	0	6	35	8	8	120405	80080	240000	80100	120333	120321	120456	120322	120327

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	120042	931	0	0	0	0	0	12	3	0	0	120036	16	16	0	25	320010	80010	240000	80010	240000	470198	5519424	0	120028	120040	120042	89977	3	90020	320010	20	240000	20	560000	120042	120051	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	794	240002	2	34	0	0	0	0	0	5020	10	16	10	8	120039	80000	240000	80010	120276	120041	120309	120177	120181
240024	120174	931	0	0	1	3	2	264	179	0	0	120166	16	0	221	75	320205	80085	240120	80123	240324	470564	5534340	0	120308	120319	120436	90257	17	92113	323348	20	242758	20	560280	120573	120309	4	1	80021	10	9	10	10	80000	80000	10	240060	0	34	28	2	240182	0	2	1560	240122	2	34	0	0	0	0	0	5044	8	16	6	9	120047	80000	240000	80010	120043	120043	120043	120043	120043
240024	120042	930	0	0	0	0	0	0	3	0	0	120035	16	16	0	25	320010	80010	240000	80010	240000	470203	5519424	0	120017	120042	120040	89977	3	90020	320010	20	240000	20	560000	120042	120049	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	2	240000	2	34	0	0	0	0	0	5020	8	16	9	8	120039	80000	240000	80010	120043	120043	120043	120043	120041
240025	120040	930	0	0	0	0	0	96	3	0	0	120025	0	16	0	25	320010	80010	240000	80010	240000	470198	5519424	0	120017	120042	120040	89985	3	90132	320010	20	240000	20	560000	120040	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	0	240002	1	0	2	240002	2	34	0	0	0	0	0	5020	6	16	8	7	120047	80000	240000	80010	120043	120052	120043	120043	120043
240024	120042	931	0	0	0	0	0	6	3	0	0	120027	16	16	0	25	320010	80010	240000	80010	240000	470198	5519760	0	120017	120050	120042	89977	3	90029	320010	20	240000	20	560000	120040	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	8	240002	0	34	0	0	0	0	0	5020	9	16	6	9	120037	80000	240000	80010	120043	120043	120043	120043	120043
240024	120049	930	0	0	0	0	0	0	9	0	0	120025	16	16	3	25	320010	80010	240000	80010	240000	470195	5519424	0	120017	120042	120051	89989	3	90020	320010	20	240000	20	560000	120040	120051	1	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	0	240002	0	0	11	240002	2	34	0	0	0	0	0	5020	8	16	9	10	120039	80000	240000	80010	120043	120050	120043	120043	120043
240024	120042	931	0	0	0	0	0	21	9	0	0	120027	16	16	0	25	320010	80010	240000	80010	240000	470198	5519424	0	120015	120040	120049	89975	3	90020	320010	20	240000	20	560000	120040	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	1	0	2	240002	2	34	0	0	0	1	0	5020	4	16	5	8	120039	80000	240000	80010	120043	120041	120041	120118	120052
240024	120049	930	0	0	0	0	0	0	6	0	0	120100	16	16	0	25	320010	80010	240000	80010	240000	470198	5519424	1	120017	120040	120049	89977	3	90022	320010	20	240000	20	560000	120040	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240000	1	0	11	240002	2	34	0	0	1	0	0	5020	9	16	8	8	120039	80000	240000	80010	120041	120043	120043	120051	120041
240024	120042	931	0	0	0	0	0	12	6	0	0	120035	16	16	0	25	320010	80010	240000	80010	240000	470193	5519424	0	120017	120040	120051	89977	3	90022	320010	20	240000	20	560000	120040	120050	1	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	0	240002	2	0	2	240000	0	34	0	0	0	0	0	5020	6	16	10	8	120048	80000	240000	80010	120043	120052	120041	120041	120043
240024	120042	930	0	0	0	0	0	0	3	0	0	120025	16	16	0	25	320010	80010	240000	80010	240000	470193	5519424	0	120015	120042	120042	89977	3	90022	320010	20	240000	20	560000	120042	120050	1	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	0	240002	0	0	8	240002	2	34	0	0	0	0	0	5020	9	16	9	10	120039	80000	240000	80010	120043	120050	120043	120043	120043

ST1 (multiple, post-index, 3 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations