Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, post-index, 3 regs, 8B)

Test 1: uops

Code:

  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f2223243a3f464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
63006295912380290250000100047232925100187694000100010002000100010002000500015903800052178129188295503104000200010005000200029533295691161001100010002000060200000320000400013129943568993174167020943334138221163672879110001658313380144962000100010002968829679297372967129676
63004295982380290210001500004715293531018531400010001000200010001000200050001590380001321722293972968231040002000100050002000296402955211610011000100020000422000093902004000014113149927269093149147220996328538281961652908410011629213293143412000100010002967829859297342978029525
63004297862390261220112761000472729526201866640041000100020021000100320105000159058000321958296222994318180400020001000500020002964329485116100110001000200200220021943020020402013045929268393109135921004323138212162652902910011634113328146302000100010002975829933298832991829687
630042998323903012903326717700046182935321186994000100010002000100010002000500015900800011217712948829660331224000200010005000200029915299321161001100010002000060200000030500600012976967069043128186420781322538151960582880110001634213398146022000100010002941829459294712946229517
63004295352370280260003100047162927711184044000100010002000100010002000500015899800012168129161293213104000200010005000200029244293141161001100010002000060200010320000600013218937569033182196920721328338141857612861110011618813213143092000100010002936029414294002938429452
63004293852270280310000100045872908811183734000100010002000100010002000500015899800052173629137295093104000200010005000200029405292302161001100010002000060200000620000000013275937768593097166420684322038131261682869010001613713143143102000100010002937229340293562937929351
630042938822802902700101000471629256101830440041000100020001000100020005000158998000102174728979294733104004200010005000200229274294211161001100010002000060200200020000600013057937569253121196620640322938161365672869710001624413285144152000100010002935829392292662936129403
630042944922902202800001000470729240211851240001000100020001000100020025000159058000122171929114294313104000200010005000200029350293551161001100010002000060200000020000400013271924668953109167020645325138081861642869610001615213320144212000100010002942729394294202953629477
630042940322902712300001000467229193011841040001000100020001000100020005000159278000102170529064295223104000200010005000200029421293001161001100010002000040200000020000600013188930069273115146520806337638191559622870710001623313309145742000100010002946129266294232949929580
63004294462280250290011210004766291811118380400010001000200010001000200050001590780001021730290312943431040002000100050002000292792937311610011000100020000402000000200006000131039291697831061210620600319537472171652824710001580912593140002000100010002887929037288522887428915

Test 2: throughput

Count: 8

Code:

  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f24373a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
24020680042620000000123049080028000253201338010080030160000801638000016000010307493679541640115800188005080204499563500103201002001600008000020040000016000080044800431180201100991001008000080000100160000042001600000002160002242000511011611800408141516000080000801008004480044800418004480044
2402048004362000000003038080038016025320123801008002116000080100800001600001190669367954164007180019800438004349956350002320100200160000800002004000001600008042380417118020110099100100800008000010016000000001600020002160000242000511011611800398000016000080000801008004480044800448004480044
240204800436200001000301108002516160253201368010080777160000801008000016000018302863679541640119800188004380042499563500013201002001600008000020040000016000080043802051180201100991001008000080000100160000042001600020006160002242000511011611800408000016000080000801008004480041800448004480044
240204800436200000000402508002716160253201278010080023160000801008000016000018302863686102640139800278004380152499563500003201002001600008000020040000016000080042800431180201100991001008000080000100160000042001600020002160002042000511011611800378000016000080000801008004480050800448004480043
240204800426200000000002608002816160253201148010080030160000801008000016000018302863679637640110800188004080043499563500013201002001600008000020040000016000080043800531180201100991001008000080000100160000042001600020002160002242000511011611800378000016000080000801008004380041800448004480044
2402048004062112100001100561800481616106253208488010080995160000801008000016000097078936800456425908002980049800634996735000732010020016000080062200400000160000800488005411802011009910010080000800001001600151544001600160101616000216441410511011611800508000016000080000801008005080050800538004480044
240204800436210000000001508002816160253201218010080033160000801008000016010818302863679541642174800188004380040499563500013201002001600008000020040000016000080043800401180201100991001008000080000100160062042001600020002160000242000512311611800398000016000080000801008004380044800448004480044
240204800436200000000302508002816160253201108010080044160000801008000016000018302863679541640094800188004380043499563501333201002001600008000020040000016000080042800401180201100991001008000080000100160000006501600020002160002242000511011611800408000016000080000801008004480043800448004480044
2402048004262100000000026080025016025320143801008004516000080100800001600001830286367954164019280018800428004349956350001320100200160000800002004000001600008004380043118020110099100100800008000010016000000001600000002160002242000511011611800408000016000080000801008004480044800438015480044
240204800436200000000302308002816160253201218010080010160000801008000016000018302863679589640089800188004280043499663500003201002001600008006120040000016000080042800431180201100991001008000080000100160000042001600020002160004242000511011621800408000016000080000801008004380043800448004580041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f222324373a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafatomic or exclusive fail (b4)bcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
24002780052620111000003000550180043160125320016800108058416000080010800001600001369990367980564292208003380052800514998435003832001020160000800002040030516000080061800481180021109101080000800001016001515010160014011416000201601410502020162121800558000016000080000800108005480059800488005080060
240024800586211000000010900075818004601672532086980010805161600008001080059160000136999036799256418420800248005080051501083500413200102016000080000204000001600008005380053118002110910108000080000101600141436001600161117160002016361410502019151919800498000016000080000800108004980059800498005280050
2400248004962010001000180001206180035000253200118001080198160000800108000016000063058436802616432630800248005180058499963500333200102016000080000204000001600008005880227118002110910108000080000101600141436001600160123160002016361410502015151618800488000016000080000800108046780481802168005380214
24002480058620111010113221000536180374160117493206698012981537160180800708005916032411176313687014641648080027800598022449993350173320010201601228000020400614160000800508021711800211091010800008000010160074143666316007600968160122016381430503420251818802138005816000080000800108055580219802268055680219
2400248038462210000111321020004100800291600253200128001080003160000800108000016000012902273679853641993080018800498004249978350020320010201600008000020400000160000800438004311800211091010800008000010160000034001600020021600020234000502020161121800398000016000080000800108004480044800438004380051
2400248004962100000000300000800281616025320016800108000216000080010800001600001290239367954164165608002580043800434997835002232001020160000800002040000016000080042800421180021109101080000800001016000003400160002005160002020000502014162012800408000016000080000800108004380043800448004480049
24002480040621000000003000208002716160253200108001080000160000800108000016000018297693679541640003080018800408004049985350023320010201600008000020400000160000800408004311800211091010800008000010160000034001600001001600020234000502020151918800468000016000080000800108004380041800448004180050
2400248004962100000000300040800271616025320011800108000016000080010800001600001829769367954164000808001880042800424998435002932001020160000800002040000016000080043800401180021109101080000800001016000003400160004102160002020000502018162011800398000016000080000800108004480044800438004380043
24002480042620000000003000108003416160253201968001080001160000800108000016000018297693679541640000080018800408004049978350023320010201600008000020400000160000800428004211800211091010800008000010160000034001600020001600000234000502019151918800408000016000080000800108004380044800448004480043
2400248005062000000000000079108003416160253200168001080005160000800108000016000018297693679541640012080018800438004349978350030320010201600008000020400000160000800428004211800211091010800008000010160000034001600020021600020234000502018162019800398000016000080000800108004480050800438004380041