Firestorm: ST1 (multiple, post-index, 4 regs, 16B) measurements

Code:

  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
64005	29290	235	1	0	4	0	4	0	0	0	6	5	0	4772	29149	0	0	23169	5000	1000	4000	1000	4000	5000	21608	5	17053	28686	29299	3	10	5000	4000	9000	29354	29251	1	1	61001	1000	1000	4005	4	12	1	4004	0	1	4	4000	0	12	0	0	0	13161	9505	6980	3099	1	49	20299	3254	3813	12	48	49	28656	1000	16135	13220	14033	4000	1000	29385	29319	29359	29472	29401
64004	29219	237	0	1	2	0	3	1	0	0	6	4	0	4763	29180	4	4	23177	5000	1000	4000	1000	4000	5000	21608	2	17028	28599	29423	3	10	5000	4000	9000	29303	29278	1	1	61001	1000	1000	4005	5	12	1	4004	0	1	8	4000	4	12	4	0	0	13071	9349	6961	3171	0	44	20359	3250	3815	12	38	46	28712	1000	16293	13096	14574	4000	1000	29317	29470	29306	29437	29320
64004	29333	235	0	0	3	0	3	0	0	0	18	0	0	4665	29033	0	0	23201	5000	1000	4000	1000	4000	5000	21629	1	17017	28651	29486	3	10	5000	4000	9000	29295	29283	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	0	4000	0	12	0	0	0	13267	9404	6997	3176	1	38	20448	3250	3816	13	38	44	28741	1000	16189	13172	14254	4000	1000	29455	29504	29339	29338	29332
64004	29312	236	0	0	2	0	2	0	0	0	0	1	0	4718	29212	0	0	23207	5000	1000	4000	1000	4000	5000	21620	4	17044	28703	29425	3	10	5000	4000	9000	29318	29342	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	3	4000	0	12	0	0	0	13222	9488	6995	3157	1	42	20420	3287	3817	17	44	40	28650	1000	16224	13166	14446	4000	1000	29340	29487	29471	29289	29247
64004	29327	235	0	1	2	0	3	1	0	0	0	5	0	4721	29075	4	4	23256	5000	1000	4000	1000	4000	5000	21619	2	17019	28662	29446	3	10	5000	4000	9000	29217	29154	1	1	61001	1000	1000	4005	5	0	1	4004	0	0	4	4000	4	12	4	1	0	13388	9254	6893	3169	1	45	20345	3199	3813	12	42	40	28606	1000	16158	13155	14459	4000	1000	29239	29481	29448	29355	29398
64004	29348	235	0	0	1	0	3	0	0	0	0	1	0	4648	29099	0	0	23334	5000	1000	4000	1000	4000	5000	21611	4	17050	28750	29452	3	10	5000	4000	9000	29271	29250	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	0	4000	0	12	0	0	0	13173	9476	6994	3127	0	45	20392	3180	3813	11	45	42	28663	1000	16066	13165	14348	4000	1000	29381	29434	29463	29335	29478
64004	29447	237	0	0	4	0	4	0	0	0	0	1	0	4645	29087	0	0	23218	5000	1000	4000	1000	4000	5000	21614	3	17029	28643	29366	3	10	5000	4000	9000	29397	29228	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	0	4000	0	0	0	0	0	13140	9430	6886	3137	0	44	20387	3281	3810	5	39	46	28605	1000	16390	12804	14264	4000	1000	29293	29252	29442	29267	29559
64004	29509	236	0	1	1	1	2	1	0	0	3	5	0	4634	29115	4	4	23366	5000	1000	4000	1000	4000	5000	21614	3	17051	28507	29378	3	10	5000	4000	9000	29247	29183	1	1	61001	1000	1000	4008	4	0	1	4004	0	1	4	4000	4	16	4	1	0	13144	9375	6930	3174	1	43	20415	3367	3810	14	40	47	28654	1000	16160	13052	14241	4000	1000	29255	29400	29432	29478	29385
64004	29293	236	0	0	1	0	2	0	0	0	24	1	0	4814	29103	0	0	23213	5000	1000	4000	1000	4000	5000	21618	3	17025	28660	29416	3	10	5000	4000	9000	29204	29286	1	1	61001	1000	1000	4000	0	0	0	4000	0	0	0	4000	2	12	0	0	0	13260	9339	6903	3102	1	41	20451	3264	3814	14	41	38	28650	1000	16202	13112	14462	4000	1000	29361	29318	29524	29383	29326
64004	29425	236	0	1	3	1	3	0	0	0	0	5	0	4622	29100	0	0	23309	5000	1000	4000	1000	4000	5000	21615	5	17042	28592	29341	3	10	5000	4000	9000	29121	29184	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	3	4000	0	12	0	0	0	13261	9512	6952	3160	0	45	20451	3227	3814	17	45	41	28617	1000	16271	13213	14147	4000	1000	29352	29328	29335	29386	29463

Count: 8

Code:

  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	160042	1285	0	0	0	0	0	0	0	3	1	0	0	0	160027	16	16	516	209	400992	80303	320420	80332	320864	477415	7393060	0	160964	0	160514	160994	80675	3	80032	400237	200	321080	202	721080	160976	161124	7	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320002	0	0	2	320000	2	0	0	0	5110	2	17	1	1	160037	80000	320000	80100	160051	160051	160186	160041	172130
320204	172339	1404	0	0	1	1	1	0	423	0	0	0	0	0	160036	0	0	85	25	400100	80100	320060	80100	320000	452853	7359856	0	160134	123	160040	160176	79988	13	80503	400237	200	320120	200	720000	160063	160054	3	1	80201	100	99	100	100	80000	80000	100	320015	17	44	0	1	320076	1	0	18	320002	16	44	14	0	5121	2	26	1	1	160168	80000	320000	80100	160190	160055	160189	160055	160184
320204	160054	1242	1	0	0	0	0	1	132	19	0	0	1	1	160049	16	16	74	53	400100	80129	320060	80100	320000	462343	7360460	0	160148	0	160185	160054	79992	3	80132	400237	200	320000	200	720270	160177	160047	2	1	80201	100	99	100	100	80000	80000	100	320014	14	44	0	0	320016	0	0	16	320002	16	44	14	0	5110	2	17	1	1	160051	80000	320000	80100	160065	160064	160055	160055	160055
320204	160053	1241	1	1	0	0	0	0	0	18	0	0	0	1	160037	16	16	4	25	400100	80100	320000	80100	320000	400519	7359908	0	160027	0	160053	160052	80002	3	80033	400100	200	320000	200	720000	160054	160052	1	1	80201	100	99	100	100	80000	80000	100	320077	15	44	29	0	320016	3	1	24	320002	2	34	0	0	5110	1	17	1	1	160039	80000	320000	80100	160043	160043	160043	160043	160043
320204	160043	1294	0	0	0	0	0	1	144	3	0	0	1	0	160027	16	16	0	53	400189	80100	320000	80129	320108	400526	7364284	1	160018	0	160042	160177	79980	3	80119	400100	200	320000	200	720000	160179	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320002	2	0	758	320002	2	42	0	0	5133	1	17	1	1	160064	81163	320000	80100	160044	160043	160043	160314	160310
320204	160086	1291	0	0	0	0	0	1	12	91	0	0	1	0	160025	16	16	1	54	400189	80100	320000	80100	320000	480499	7359448	0	160017	0	160042	160042	79978	3	80025	400100	202	320120	200	720000	160042	160054	2	1	80201	100	99	100	100	80000	80000	100	320000	0	42	0	0	320002	1	0	790	320062	2	42	0	0	5121	4	26	2	1	160039	80029	320000	80100	160043	160043	160043	160177	160188
320204	160040	1295	0	1	0	0	1	0	153	3	0	0	1	0	160036	16	16	0	25	400100	80158	320000	80100	320000	461183	7359424	0	160017	0	160042	160177	80057	12	80024	400100	200	320000	200	720000	160040	160040	2	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	2	0	750	320002	2	0	0	0	5110	1	17	1	1	160277	80058	320000	80100	160185	160051	160059	160051	160043
320204	160042	1295	0	0	1	0	2	0	153	97	0	0	0	0	160027	16	16	0	74	400100	80160	320120	80100	320216	400524	7369312	0	160490	0	160050	160042	79980	3	80024	400100	200	320120	200	720000	160051	160173	2	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	0	0	2	320002	0	0	0	0	5110	1	17	1	1	160037	80000	320000	80100	160041	160050	160041	160041	160043
320204	160040	1285	0	0	0	0	0	0	3	6	0	0	0	0	160027	16	16	0	25	400100	80100	320000	80100	320000	400524	7359424	0	160017	0	160040	160042	79978	3	80024	400100	200	320000	200	720000	160042	160054	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320002	9	0	5	320002	2	34	0	0	5110	1	17	1	1	160039	80000	320000	80100	160043	160043	160043	160043	160051
320204	160042	1285	0	0	0	0	0	0	15	3	0	0	0	0	160025	0	16	0	25	400100	80100	320000	80100	320000	400524	7359424	0	160017	0	160040	160040	79980	3	80024	400100	200	320000	200	720000	160050	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320002	0	0	5	320002	2	34	0	0	5110	1	17	1	1	160037	80000	320000	80100	160041	160052	160041	160052	160043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	160042	1241	0	0	1	0	0	0	276	3	1	0	0	160025	16	16	0	25	400010	80010	320000	80039	320000	400074	7364140	160017	160049	160042	79980	3	80032	400010	20	320000	20	720000	160042	160050	1	1	80021	10	9	10	10	80000	80000	10	320015	14	34	0	0	320002	0	0	2	320062	2	34	0	5020	3	17	3	3	160157	80000	0	320000	80010	160043	160043	160043	160043	160180
320024	160063	1240	0	0	0	0	0	0	351	3	0	0	0	160043	16	16	0	53	400010	80039	320000	80010	320000	400074	7359808	160017	160050	160042	79980	3	80024	400010	20	320000	20	720000	160051	160171	1	1	80021	10	9	10	10	80000	80000	10	320000	2	38	0	0	320002	0	0	16	320002	2	34	0	5020	3	17	3	4	160056	80000	0	320000	80010	160041	160136	160043	160043	160043
320024	160174	1240	0	0	0	0	0	0	75	91	1	0	0	160025	16	0	0	47	400010	80010	320000	80010	320000	400074	7359352	160143	160042	160050	79988	3	80131	400010	20	320000	20	720000	160175	160191	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	0	320002	0	0	18	320002	0	34	0	5020	2	17	3	2	160167	80000	0	320000	80010	160041	160043	160041	160176	160043
320024	160042	1241	0	0	0	0	1	0	48	3	0	0	0	160027	16	16	0	25	400010	80010	320000	80010	320000	480049	7359808	160025	160042	160050	80064	3	80033	400010	20	320000	20	720000	160042	160051	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	0	320002	0	0	0	320002	2	34	0	5020	3	17	3	3	160039	80000	0	320000	80010	160043	160043	160043	160043	160043
320024	160042	1241	0	0	0	0	0	0	0	182	0	0	0	160027	16	0	0	46	400010	80010	320000	80010	320000	400074	7364572	160017	160042	160042	79980	3	80121	400010	20	320120	20	720270	160317	160174	2	1	80021	10	9	10	10	80000	80000	10	320180	0	34	58	2	320185	0	0	3063	320182	2	34	2	5056	4	53	3	4	160397	80029	0	320000	80010	163287	163793	161209	160434	160437
320024	160447	1244	1	0	1	0	4	3	729	355	0	0	0	160034	16	16	374	25	400010	80010	320000	80010	320000	480049	7359352	160017	160051	160042	79980	3	80024	400010	20	320000	20	720000	160042	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	0	320002	0	0	8	320002	2	34	0	5020	2	17	3	3	160039	80000	0	320000	80010	160043	160043	160050	160052	160043
320024	160049	1241	0	0	0	0	0	0	12	0	0	0	0	160027	16	16	0	25	400010	80010	320000	80010	320000	400074	7359424	160017	160042	160040	79980	3	80024	400010	20	320000	20	720000	160040	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	0	0	320002	1	0	5	320002	2	34	0	5020	3	17	3	3	160047	80000	0	320000	80010	160043	160043	160043	160043	160051
320024	160042	1240	0	0	0	0	0	0	309	6	0	0	0	160027	16	16	0	25	400010	80010	320000	80010	320000	400074	7359424	160017	160042	160042	79980	3	80024	400010	20	320000	20	720000	160042	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	0	320002	0	0	2	320002	2	34	0	5020	3	17	3	3	160047	80000	0	320000	80010	160043	160041	160043	160041	160052
320024	160042	1241	0	0	0	0	0	0	9	3	0	0	0	160027	16	16	0	25	400010	80010	320000	80010	320000	400074	7359352	160025	160040	160050	79989	3	80069	400010	20	320000	20	720000	160040	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	0	320002	1	0	8	320002	0	36	0	5020	3	17	3	3	160047	80000	0	320000	80010	160043	160043	160041	160043	160041
320024	160040	1241	0	0	0	0	0	0	9	0	1	0	0	160027	16	16	0	25	400010	80010	320000	80010	320000	400074	7359424	160017	160042	160042	79980	3	80024	400010	20	320000	20	720000	160042	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	0	0	320002	0	0	2	320002	2	34	0	5020	3	17	3	3	160039	80032	0	320000	80010	160043	160043	160043	160041	160043

ST1 (multiple, post-index, 4 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations