Firestorm: ST1 (multiple, post-index, 4 regs, 2D) measurements

Code:

  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5e	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
64005	29255	235	2	1	5	2	4	2	0	0	279	181	0	0	0	4711	28781	0	0	23077	5010	1001	4004	1001	4000	5005	21775	0	13	0	17114	28435	29218	8	30	5005	4004	9000	29026	29066	3	1	61001	1000	1000	4014	7	8	0	3	4004	1	1	854	4004	4	8	4	6	0	13075	9367	6934	3097	1	63	20072	3228	3820	23	57	63	28540	1000	15927	12620	14258	4000	1000	29250	29194	29101	29315	29334
64004	29217	235	0	1	1	2	1	0	2	2	135	269	0	0	0	4653	29128	0	0	23090	5005	1001	4004	1001	4008	5000	21768	0	4	0	17085	28517	29179	15	49	5005	4000	9009	29031	28992	2	1	61001	1000	1000	4007	18	12	0	3	4004	0	0	396	4000	4	0	4	3	246	13232	9137	6814	3168	1	60	20288	3229	3815	15	63	59	28379	1000	15591	12796	14063	4000	1000	28961	28946	29062	28925	28891
64004	28924	233	0	1	0	1	0	0	0	0	0	5	0	0	0	4736	28751	0	0	22800	5000	1000	4000	1000	4000	5000	21623	0	6	0	17029	28292	28776	3	10	5003	4000	9000	28759	28899	1	1	61001	1000	1000	4004	4	8	0	1	4004	0	0	103	4000	4	8	4	1	0	13280	9441	6880	3188	0	58	19886	3303	3817	16	60	64	28322	1000	15772	12920	14162	4000	1000	29030	28937	29057	29032	28830
64004	29064	233	0	1	0	0	0	1	0	0	3	4	0	0	0	4635	28783	0	0	22817	5000	1000	4000	1000	4000	5000	21627	0	4	0	17056	28372	28908	3	28	5000	4000	9000	28977	28918	1	1	61001	1000	1000	4005	6	8	0	1	4004	0	2	97	4000	4	8	4	1	0	13146	9369	6960	3157	1	60	19975	3208	3810	10	56	52	28406	1000	15607	12584	14153	4000	1000	28963	28813	29021	28936	29003
64004	28914	233	0	1	0	0	0	1	0	0	3	5	0	0	0	4672	28807	0	0	22939	5000	1000	4000	1000	4000	5000	21613	0	11	0	17061	28303	28788	3	10	5000	4000	9000	28797	28992	2	1	61001	1000	1000	4005	5	8	0	1	4004	0	10	124	4000	4	0	4	1	0	13131	9216	6997	3134	0	53	19929	3278	3807	17	62	70	28391	1000	15734	12628	13961	4000	1000	28975	28908	28922	29021	28988
64004	29064	233	0	1	0	1	0	0	0	0	3	5	0	0	0	4780	28731	0	0	22830	5000	1000	4000	1000	4000	5000	21619	0	2	0	17039	28314	28991	3	10	5000	4000	9000	28857	28835	1	1	61001	1000	1000	4005	4	8	0	1	4004	0	0	19	4000	4	0	4	1	0	13053	9327	6997	3145	0	55	19958	3201	3815	18	65	61	28360	1000	15735	12577	13633	4000	1000	29059	29075	28961	29023	28991
64004	28940	233	0	1	0	2	1	1	0	0	3	5	0	0	0	4687	28808	0	0	22840	5000	1000	4000	1000	4000	5000	21610	0	2	0	17044	28334	28964	3	10	5000	4000	9000	28827	28804	1	1	61001	1000	1000	4004	5	0	0	3	4006	1	2	97	4000	4	0	4	2	0	13079	9352	6942	3218	2	56	19978	3177	3814	11	60	65	28210	1000	15745	12512	13911	4000	1000	28970	28904	29009	28950	28891
64004	29061	232	0	1	0	1	0	0	0	0	3	4	0	0	0	4726	28777	2	0	22956	5000	1000	4000	1000	4000	5000	21629	0	0	0	17054	28416	28958	3	10	5000	4000	9000	28868	28867	1	1	61001	1000	1000	4005	4	8	0	1	4004	1	1	114	4000	6	12	4	0	0	13145	9319	6973	3152	1	45	19834	3238	3819	7	68	61	28382	1000	15666	12584	14206	4000	1000	28947	28967	29018	29050	28929
64004	28987	233	0	1	1	1	1	1	0	0	3	93	0	0	0	4671	28813	0	2	22827	5000	1000	4000	1000	4004	5000	21632	0	4	0	17015	28261	28872	3	10	5000	4000	9000	28868	28841	1	1	61001	1000	1000	4005	6	12	0	1	4004	0	1	100	4002	6	8	4	2	0	13185	9189	7009	3100	0	62	19968	3190	3818	17	61	62	28413	1000	15902	12747	13857	4000	1000	29044	28940	29090	28908	28943
64004	29039	231	0	1	2	1	1	1	0	0	9	5	0	0	0	4684	28801	0	0	22828	5000	1000	4004	1001	4000	5000	21624	0	4	0	17057	28148	28934	3	10	5000	4004	9000	28832	28884	1	1	61001	1000	1000	4005	5	12	0	0	4004	0	2	28	4000	4	8	4	1	0	13129	9144	6863	3178	0	58	19954	3209	3811	16	64	64	28208	1000	15740	12511	13993	4000	1000	28893	28952	28873	29046	28991

Count: 8

Code:

  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	160043	1240	0	0	0	0	0	0	0	3	0	0	0	0	160028	16	0	0	25	400100	80100	320000	80100	320000	400526	7359352	1	160017	0	160042	160040	79978	3	80024	400100	200	320000	200	720000	160042	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	42	0	0	320000	0	0	0	320002	2	0	5110	0	1	17	1	1	160039	80000	320000	80100	160043	160043	160055	160043	160043
320204	160042	1240	0	0	0	0	0	0	0	3	1	0	0	1	160028	0	16	0	25	400100	80100	320000	80100	320000	400526	7359352	0	160015	0	160040	160042	79981	3	80022	400100	200	320000	200	720000	160040	160040	1	1	80201	100	99	100	100	80000	80000	100	320000	0	42	0	0	320000	1	0	5	320000	2	42	5110	0	2	17	1	1	160039	80000	320000	80100	160043	160043	160044	160043	160043
320204	160042	1241	0	0	0	0	0	0	0	3	1	0	0	1	160027	0	16	0	25	400100	80100	320000	80100	320000	470176	7383532	0	160017	0	160054	160042	79981	3	80024	400100	200	320000	200	720000	160040	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	42	0	0	320000	0	0	2	320002	2	42	5110	0	2	17	1	2	160039	80000	320000	80100	160041	160041	160043	160044	160041
320204	160180	1285	0	0	0	0	0	0	0	3	0	0	1	0	160028	16	16	0	25	400189	80100	320000	80100	320000	480499	7359352	0	160017	0	160042	160042	79980	3	80025	400100	200	320000	200	720000	160042	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	48	0	0	320002	0	0	2	320002	0	0	5110	0	2	17	2	2	160039	80000	320000	80100	160044	160041	160044	160175	160043
320204	160054	1240	0	0	0	0	0	0	12	3	0	0	0	1	160027	16	16	0	25	400100	80100	320000	80100	320000	400526	7359352	0	160017	0	160175	160042	79980	3	80024	400100	200	320000	200	720000	160043	160043	1	1	80201	100	99	100	100	80000	80000	100	320060	0	42	0	0	320000	1	0	5	320062	0	0	5110	0	2	17	2	2	160040	80000	320000	80100	160043	160044	160043	160041	160173
320204	160043	1240	0	0	0	0	0	0	0	3	0	0	0	1	160166	16	16	1	25	400100	80100	320000	80100	320108	400526	7359448	0	160017	0	160042	160042	79981	3	80024	400100	200	320000	200	720000	160043	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	42	0	0	320000	1	0	2	320002	0	42	5112	0	2	17	2	2	160040	80000	320000	80100	160043	160043	160044	160041	160041
320204	160040	1241	0	0	0	0	0	0	0	3	0	0	1	0	160025	16	16	1	25	400100	80129	320000	80100	320000	400526	7359448	0	160017	0	160174	160042	79980	3	80024	400100	200	320000	200	720000	160043	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	42	0	0	320002	0	0	5	320002	2	42	5110	0	1	17	1	2	160039	80029	320000	80100	160041	160191	160043	160043	160043
320204	160040	1285	0	0	0	0	0	0	9	3	0	0	0	0	160027	16	16	1	25	400100	80100	320000	80100	320000	400526	7359448	0	160017	0	160171	160042	79980	3	80022	400100	200	320000	200	720000	160043	160040	1	1	80201	100	99	100	100	80000	80000	100	320062	0	0	0	0	320002	0	0	2	320060	2	0	5112	0	2	17	2	1	160039	80000	320000	80100	160041	160043	160041	160043	160044
320204	160042	1241	0	0	0	0	0	0	0	0	0	1	0	0	160025	16	16	1	25	400100	80100	320000	80100	320000	480499	7359352	0	160017	0	160170	160432	79981	3	80214	400237	200	320120	200	720270	160042	160043	1	1	80201	100	99	100	100	80000	80000	100	320180	2	0	979	0	320180	0	9	3127	320182	2	42	5143	0	2	26	2	1	164477	80087	320000	80100	160315	160314	160460	160572	160442
320204	160444	1244	1	1	1	0	3	3	528	267	0	1	0	1	160027	0	16	1	25	400100	80100	320000	80100	320000	400526	7359352	0	160017	0	160042	160043	79978	3	80025	400100	200	320000	200	720000	160042	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	42	0	0	320000	1	0	3	320000	0	42	5112	0	2	17	2	1	160037	80000	320000	80100	160043	160044	160043	160041	160041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	160458	1241	1	1	0	1	0	0	102	0	1	164122	16	16	296	107	400277	80097	320120	80126	320216	444876	7369604	0	160274	160534	160448	80145	14	80292	400421	20	320480	20	720000	160052	160054	1	1	80021	10	9	10	10	80000	80000	10	320014	15	44	0	1	320016	0	2	17	320002	16	44	14	0	5020	4	17	6	6	160051	80000	0	320000	80010	160053	160054	160054	160053	160053
320024	160054	1241	1	0	0	0	0	0	17	0	1	160037	16	16	6	25	400010	80010	320000	80010	320000	400069	7359956	0	160039	160053	160063	80001	3	80034	400010	20	320000	20	720000	160054	160052	1	1	80021	10	9	10	10	80000	80000	10	320015	14	44	0	1	320016	0	0	19	320000	16	44	14	0	5020	7	17	7	7	160060	80000	0	320000	80010	160055	160055	160055	160055	160065
320024	160054	1241	1	1	0	0	0	0	18	0	1	160039	16	16	2	25	400010	80010	320000	80010	320000	400069	7360028	0	160029	160052	160054	79992	3	80045	400010	20	320000	20	720000	160053	160052	1	1	80021	10	9	10	10	80000	80000	10	320015	14	42	0	0	320016	0	0	16	320002	16	44	14	1	5020	7	17	7	7	160051	80000	0	320000	80010	160064	160065	160064	160053	160055
320024	160053	1241	1	1	1	0	0	0	20	0	1	160042	16	16	0	25	400010	80010	320000	80010	320000	400069	7360004	0	160027	160052	160063	80031	3	80035	400010	20	320000	20	720000	160054	160054	1	1	80021	10	9	10	10	80000	80000	10	320014	14	44	0	0	320016	0	0	18	320002	16	44	14	1	5020	7	17	7	7	160044	80000	0	320000	80010	160055	160055	160065	160064	160056
320024	160597	1242	1	1	0	0	1	0	2411	0	1	160039	16	16	1	25	400010	80010	320000	80010	320000	400068	7360028	0	160029	160047	160054	79985	3	80030	400010	20	320720	20	722700	160054	161607	12	1	80021	10	9	10	10	80000	80000	10	320015	16	44	0	0	320016	0	1	18	320002	16	0	14	0	5020	5	17	7	5	160060	80000	0	320000	80010	160325	160055	160191	160055	160063
320024	160054	1241	1	0	0	0	0	150	17	0	1	160046	16	16	2	49	400010	80010	320000	80010	320000	474401	7359908	0	160030	160054	160047	79985	3	80036	400010	20	320000	20	720000	160197	160184	2	1	80021	10	9	10	10	80000	80000	10	320014	14	44	0	0	320016	0	0	14	320002	16	44	14	1	5020	7	16	7	5	160049	80000	0	320000	80010	160055	160055	160055	160055	160055
320024	160052	1241	1	0	0	0	0	0	19	0	1	160039	16	0	1	25	400010	80010	320060	80010	320000	400069	7360004	0	160029	160052	160047	79985	3	80034	400010	20	320000	20	720000	160054	160052	1	1	80021	10	9	10	10	80000	80000	10	320014	14	44	0	0	320016	1	1	17	320002	16	44	14	0	5020	7	17	7	5	160052	80000	0	320000	80010	160450	160463	160320	160451	160324
320024	160591	1243	1	2	2	1	2	5016	3187	0	1	160563	16	16	221	102	400366	80068	320180	80097	320324	453857	7374392	0	160383	160312	160454	80148	33	80428	400558	20	320000	20	720000	160047	160052	1	1	80021	10	9	10	10	80000	80000	10	320015	15	44	1	1	320016	0	2	24	320002	16	44	14	1	5020	7	17	7	7	160044	80000	0	320000	80010	160316	160313	160187	160054	160053
320024	160047	1241	1	0	0	0	0	12	19	0	1	160039	16	16	1	25	400010	80010	320000	80010	320000	479964	7360028	0	160264	160315	160323	79990	3	80036	400010	20	320000	20	720000	160131	160054	1	1	80021	10	9	10	10	80000	80000	10	320015	14	44	0	1	320016	0	1	21	320002	16	44	14	0	5020	7	17	7	5	160049	80029	0	320000	80010	160055	160055	160048	160055	160056
320024	160054	1241	1	0	0	0	0	132	1075	0	1	160039	0	16	2	25	400010	80010	320000	80010	320000	400069	7360004	1	160029	160047	160047	79993	3	80037	400010	20	320000	20	720000	160047	160054	1	1	80021	10	9	10	10	80000	80000	10	320015	14	44	0	0	320014	0	0	19	320002	16	44	14	0	5020	7	17	5	7	160051	80000	107	320000	80010	160125	160055	160048	160055	160055

ST1 (multiple, post-index, 4 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations