Firestorm: ST1 (multiple, post-index, 4 regs, 2S) measurements

Code:

  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64006	29496	236	2	1	1	1	1	1	0	0	0	0	2	1	0	0	4721	29192	0	2	18342	5000	1000	2000	2000	1000	2000	2000	5000	21808	16000	16	21871	29139	29504	7	10	5000	2000	2000	5000	4000	29333	29341	1	1	61001	1000	1000	2003	3	8	0	2002	0	0	2	2000	0	6	0	0	0	13194	9762	6976	3178	0	38	20638	3343	3813	16	36	40	28927	1000	16283	13260	14367	2000	2000	1000	29388	29589	29499	29545	29552
64004	29661	238	0	0	0	1	1	0	0	1	1	396	88	0	0	0	4598	29336	0	2	18517	5000	1000	2000	2002	1000	2000	2000	5005	21828	16000	16	21914	29233	29574	15	30	5003	2000	2000	5005	4008	29488	29453	3	1	61001	1000	1000	2000	0	4	2	2001	0	2	495	2000	0	6	0	0	0	13102	9255	6990	3171	0	34	20503	3354	3806	19	31	32	28784	1001	16389	13220	14430	2000	2000	1000	29823	29698	29617	29631	29596
64004	29734	238	0	0	0	1	0	0	0	2	2	264	177	0	0	0	4589	29410	2	2	18373	5010	1000	2002	2002	1001	2004	2002	5000	21977	16000	10	21910	29343	29793	3	10	5000	2000	2000	5000	4000	29489	29558	1	1	61001	1000	1000	2000	0	6	0	2000	0	0	0	2000	0	6	0	0	0	13259	9552	6945	3126	0	35	20301	3382	3801	20	41	37	28795	1001	16522	13503	14754	2000	2000	1000	29317	29250	29309	29351	29644
64004	29355	236	1	0	0	0	0	0	0	0	0	0	0	0	0	0	4641	29233	2	0	18193	5000	1000	2000	2000	1000	2000	2000	5000	21802	16000	7	21934	29223	29434	3	10	5000	2000	2000	5005	4000	29380	29397	1	1	61001	1000	1000	2000	0	6	0	2000	0	0	0	2000	0	0	0	0	120	13208	9397	6882	3101	0	35	20426	3300	3813	13	36	33	28721	1000	16131	13264	14616	2000	2000	1000	29480	29351	29546	29402	29500
64004	29712	235	0	0	0	0	0	0	0	0	0	0	0	0	0	0	4654	29258	0	0	18451	5028	1000	2002	2002	1002	2002	2004	5015	21804	16032	9	22153	29670	29888	75	271	5050	2020	2012	5035	4032	29798	29850	14	1	61001	1000	1000	2013	2	0	0	2018	0	3	5477	2019	2	0	2	0	0	12799	8919	6763	3095	0	37	20985	3292	3813	57	35	41	29414	1000	16334	13354	14820	2000	2000	1000	29389	29353	29366	29313	29305
64004	29287	227	0	1	0	1	1	0	1	0	0	0	3	0	0	0	4653	29047	0	0	18206	5000	1000	2000	2000	1000	2000	2000	5000	21798	16000	13	21801	28957	29192	49	199	5000	2000	2000	5000	4000	29490	29235	1	1	61001	1000	1000	2003	3	0	1	2002	3	1	2	2000	2	8	2	3	0	13109	9474	6909	3082	0	34	20596	3096	3814	28	32	34	28911	1006	16191	13199	14285	2000	2000	1000	29567	29721	29517	29623	29692
64004	29706	230	1	1	0	2	0	0	2	6	3	936	669	1	0	0	4604	29622	0	0	18694	5080	1013	2024	2030	1012	2027	2034	5035	22235	16000	12	22265	29836	30194	107	430	5070	2031	2030	5060	4030	29967	30284	23	1	61001	1000	1000	2028	2	6	0	2028	1	0	8392	2014	2	0	2	0	0	12866	8895	6817	3031	0	40	20538	3196	3809	46	39	39	29133	1007	16541	13183	14673	2000	2000	1000	29957	30156	29998	29875	29850
64004	29828	232	0	1	0	2	2	0	0	6	6	1596	795	0	0	0	4386	30435	0	2	18645	5075	1011	2018	2028	1008	2022	2024	5060	22558	16240	12	22205	30160	30368	82	373	5070	2029	2021	5045	4020	29875	30374	19	1	61001	1000	1000	2022	2	6	3	2009	1	0	3127	2014	2	0	2	3	0	13108	9305	6870	3157	0	37	20785	3292	3810	45	33	36	29314	1007	16563	13161	14382	2000	2000	1000	29960	30046	30032	30177	29974
64004	30129	241	0	1	0	1	1	0	1	0	0	0	178	0	0	1	4738	29504	0	0	18323	5005	1000	2000	2000	1001	2000	2000	5000	21804	16016	2	21976	29196	29396	3	10	5000	2000	2000	5000	4000	29359	29240	1	1	61001	1000	1000	2003	2	6	2	2002	0	1	2	2000	2	4	2	0	0	13207	9587	6969	3124	4	42	20490	3287	3821	8	31	34	28789	1000	16258	13011	14309	2000	2000	1000	29419	29400	29458	29341	29410
64004	29368	227	0	1	3	1	0	9	1	0	0	0	3	0	0	0	4654	29208	2	0	18178	5000	1000	2000	2000	1000	2000	2000	5005	21800	16000	15	21941	29068	29387	7	10	5000	2000	2002	5000	4000	29398	29315	1	1	61001	1000	1000	2002	2	4	1	2002	0	1	222	2000	3	5	2	1	0	13329	9353	6993	3124	3	34	20427	3294	3816	16	37	36	28815	1000	16218	12985	14244	2000	2000	1000	29362	29441	29349	29539	29396

Count: 8

Code:

  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	23	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bb	bc	l1d cache miss st nonspec (c0)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320206	80050	620	0	0	0	0	1	0	0	3	0	6241	0	80030	0	16	0	25	408827	80100	165494	160000	80100	160000	160000	480499	2155574	1300349	1	80023	0	80049	80049	0	3	31	400100	200	160000	160120	200	400000	320000	80050	80045	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	0	0	0	160000	0	0	2	160002	0	0	0	0	0	5109	1	17	1	1	80043	80000	160000	160000	80100	80045	80046	80045	80212	80045
320204	80043	620	0	0	0	0	0	0	0	3	0	5003	0	80030	16	16	0	25	405081	80100	164960	160000	80100	160000	160000	480499	2398849	1295058	0	80025	0	80050	80046	0	3	32	400100	200	160000	160000	200	400000	320000	80045	80045	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	32	62	0	160002	0	0	8	160002	0	2	32	0	0	5109	1	17	1	1	80042	80000	160000	160000	80100	80045	80054	80046	80046	80050
320204	80049	620	0	0	0	0	0	0	0	3	0	8645	0	80206	16	16	0	25	404562	80100	165268	160000	80100	160000	160000	480499	2228352	1296284	0	80024	0	80045	80045	0	3	26	400100	200	160000	160000	200	400000	320000	80050	80045	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	32	0	0	160002	0	0	11	160002	0	0	0	0	0	5109	1	17	1	1	80042	80000	160000	160000	80100	80046	80051	80046	80046	80051
320204	80212	620	0	0	0	0	0	0	21	3	0	6648	0	80029	16	0	112	48	406344	80100	165007	160000	80100	160000	160000	480499	2319712	1302517	0	80025	0	80045	80045	0	3	26	400100	200	160000	160000	200	400000	320000	80045	80045	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	32	0	0	160002	1	0	0	160002	0	0	32	0	0	5109	1	17	1	1	80042	80000	160000	160000	80100	80046	80046	80051	80046	80046
320204	80045	620	0	0	0	0	0	0	0	3	0	8652	0	80030	16	16	0	25	404720	80159	165022	160000	80100	160000	160000	480499	2399093	1298888	0	80025	0	80045	80050	0	3	27	400100	200	160000	160000	200	400000	320000	80212	80044	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	32	0	0	160002	0	0	8	160002	0	2	32	0	0	5109	3	17	1	1	80197	80059	160000	160000	80100	80046	80046	80639	80561	80046
320204	80045	620	0	0	0	0	1	0	33	3	0	5917	0	80197	16	16	0	25	403868	80100	165681	160000	80159	160000	160000	480499	2232333	1295611	0	80025	0	80212	80045	0	3	31	400100	200	160000	160000	200	400000	320000	80045	80045	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	32	0	0	160002	0	0	0	160002	0	0	32	0	0	5109	1	17	1	1	80041	80000	160000	160000	80100	80046	80046	80051	80046	80046
320204	80045	620	0	0	0	0	0	0	12	2	0	5511	0	80030	16	16	0	25	405196	80100	165617	160000	80100	160000	160000	480499	2228300	1302019	0	80024	0	80045	80045	0	3	27	400100	200	160000	160000	200	400000	320000	80044	80045	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	32	0	0	160000	0	0	14	160002	0	2	0	0	0	5109	1	17	1	1	80042	80000	160000	160000	80100	80051	80046	80046	80051	80046
320204	80045	620	0	0	0	0	0	0	0	0	0	4907	0	80035	16	16	0	25	403416	80100	164568	160000	80100	160000	160000	480499	2231318	1293278	0	80024	0	80045	80045	0	3	28	400100	200	160000	160000	200	400000	320000	80045	80213	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	0	0	0	160002	1	0	0	160002	0	2	0	0	0	5109	1	17	1	1	80042	80000	160000	160000	80100	80046	80046	80051	80046	80047
320204	80044	620	0	0	0	0	0	0	12	3	0	4769	0	80030	16	16	0	25	406497	80100	166657	160000	80100	160000	160000	480499	2398801	1299695	0	80024	0	80049	80050	0	3	27	400100	200	160000	160000	200	400000	320000	80044	80045	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	0	0	0	160002	0	0	5	160002	0	2	32	0	0	5109	1	17	1	1	80043	80000	160000	160000	80100	80050	80213	80046	80046	80046
320204	80045	621	0	0	0	0	0	0	0	3	0	5194	0	80029	16	16	0	25	404475	80100	164375	160000	80100	160000	160000	480851	2230513	1298576	0	80025	0	80045	80046	0	3	32	400100	200	160000	160000	200	400000	320000	80045	80045	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	32	0	0	160002	0	0	2	160002	0	2	32	0	0	5109	1	17	1	1	80204	80000	160000	160000	80100	80051	80046	80046	80050	80046

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320026	80051	621	0	0	0	0	0	0	3	0	5312	0	80030	16	16	0	25	406158	80010	165112	160000	80010	160000	160000	480049	2225091	1290936	0	80025	80045	80045	0	3	72	400010	20	160000	160000	20	400000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	2	160002	2	40	0	5019	0	13	17	14	7	80117	80000	160000	160000	80010	80046	80046	80046	80046	80046
320024	80045	620	0	0	0	0	0	0	3	0	2745	0	80029	16	0	0	25	404155	80010	163651	160000	80010	160000	160000	480049	1919828	1302329	0	80024	80045	80045	0	3	27	400010	20	160000	160000	20	400000	320000	80045	80045	2	1	80021	10	9	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	2	160002	2	40	0	5019	0	6	17	13	14	80042	80000	160000	160000	80010	80046	80046	80047	80047	80214
320024	80045	620	0	0	0	0	0	0	3	0	5407	0	80030	16	16	0	25	404603	80010	164314	160000	80010	160000	160000	480049	2232501	1298599	0	80024	80045	80044	0	7	27	400010	20	160000	160000	20	400000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	40	0	0	160062	0	0	2	160000	2	40	0	5019	0	5	25	13	5	80042	80000	160000	160000	80010	80046	80046	80049	80047	80046
320024	80045	620	0	0	0	0	0	132	3	0	4080	0	80030	16	16	93	25	405767	80010	164458	160000	80010	160000	160000	480049	2152181	1295291	0	80024	80045	80045	0	3	27	400010	20	160000	160000	20	400300	320000	80044	80044	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160061	0	0	2	160002	2	40	0	5019	0	5	17	5	13	80198	80000	160000	160000	80010	80046	80046	80047	80214	80046
320024	80045	621	0	0	0	0	0	0	3	0	3795	0	80030	16	16	0	25	405795	80010	165551	160000	80010	160118	160000	480049	2237947	1301382	0	80024	80045	80045	84	3	27	400010	20	160000	160000	20	400000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	2	160002	2	40	0	5033	0	14	17	6	12	80042	80000	160000	160000	80010	80046	80046	80046	80046	80046
320024	80045	620	0	0	0	1	0	0	3	0	2906	0	80030	16	16	0	25	405955	80010	167117	160000	80010	160000	160000	480049	2078211	1300156	0	80024	80054	80045	0	3	27	400010	20	160120	160000	20	400000	320000	80044	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	46	0	0	160002	0	0	2	160002	2	40	0	5019	0	14	17	14	13	80042	80000	160000	160000	80010	80213	80046	80055	80046	80046
320024	80045	621	0	0	0	0	0	0	3	0	5089	0	80030	16	16	0	25	403365	80010	164858	160060	80010	160000	160000	480049	2234088	1294279	0	80029	80123	80215	0	3	36	400010	20	160000	160000	20	400000	320000	80044	80046	1	1	80021	10	9	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	2	160002	2	40	0	5019	0	13	17	7	13	80042	80000	160000	160000	80010	80046	80046	80046	80046	80046
320024	80045	621	0	0	0	0	0	0	3	0	5169	0	80030	16	16	0	25	405374	80010	165003	160000	80010	160000	160000	480049	2209669	1298873	0	80024	80045	80045	0	8	28	400010	20	160000	160000	20	400000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	2	160002	2	40	0	5019	0	13	17	11	13	80042	80000	160000	160000	80010	80049	80046	80046	80047	80046
320024	80046	621	0	0	0	0	0	0	3	0	4589	0	80030	16	16	0	25	405215	80010	164176	160000	80010	160000	160000	480049	2079382	1304780	0	80024	80045	80045	0	3	27	400010	20	160000	160000	20	400000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	5	160002	2	40	0	5019	0	16	17	6	14	80042	80000	160000	160000	80010	80055	80045	80046	80055	80046
320024	80045	620	0	0	0	0	0	0	3	0	3857	0	80029	16	16	0	25	404839	80069	165438	160000	80010	160000	160000	480049	2226998	1293428	0	80024	80045	80045	0	3	27	400010	20	160000	160000	20	400000	320000	80213	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160002	0	0	2	160002	2	40	0	5019	0	13	17	13	5	80042	80000	160000	160000	80010	80046	80045	80046	80046	80046

ST1 (multiple, post-index, 4 regs, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations