Firestorm: ST1 (multiple, post-index, 4 regs, 4S) measurements

Code:

  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
64005	28599	211	0	13	0	14	0	0	4	0	5099	28042	0	0	22066	5000	1000	4000	1000	4000	5000	21625	14	17021	27800	28385	3	10	5000	4000	9000	28295	28224	1	1	61001	1000	1000	4005	6	0	2	4006	0	1	8	4000	2	10	0	0	13881	10031	7176	3408	7	45	19292	3375	3806	7	52	40	27889	1000	14178	11989	12057	4000	1000	28333	28276	28123	28229	28177
64004	28408	212	0	13	0	11	0	0	0	1	5316	28164	0	4	22317	5000	1000	4000	1000	4000	5000	21636	10	17039	27862	28458	3	10	5000	4000	9000	28194	28092	1	1	61001	1000	1000	4000	0	10	0	4000	0	0	0	4002	2	10	0	0	13761	9820	7229	3439	7	42	19277	3349	3804	5	60	38	27903	1000	14139	11839	12204	4000	1000	28153	28495	28052	28214	28178
64004	28057	211	1	14	1	11	1	0	7	0	5200	28187	4	4	22225	5000	1000	4000	1000	4000	5000	21625	9	17014	27900	28346	3	10	5000	4000	9000	28394	28188	1	1	61001	1000	1000	4005	4	14	1	4006	0	2	7	4002	6	14	4	1	13617	9651	7176	3409	6	35	19214	3344	3802	6	52	46	27931	1000	14652	12093	12608	4000	1000	28379	28307	28238	28450	28350
64004	28287	212	0	11	0	13	0	0	3	0	5186	28341	4	0	22063	5000	1000	4000	1000	4000	5000	21640	15	17022	27887	28323	3	10	5000	4000	9000	28148	28408	1	1	61001	1000	1000	4000	0	10	0	4002	0	0	0	4002	2	0	0	0	13926	10294	7248	3332	5	43	19225	3487	3806	11	45	43	27880	1000	13795	11750	11920	4000	1000	28281	28382	28049	28276	28233
64004	28200	212	1	12	1	10	1	0	4	0	5025	27903	4	0	22128	5000	1000	4000	1000	4000	5000	21630	20	17027	27923	28302	3	10	5000	4000	9000	28285	28212	1	1	61001	1000	1000	4005	5	14	3	4006	0	1	11	4000	6	14	4	2	13294	10301	7155	3436	7	42	19484	3282	3800	12	56	47	27742	1000	14044	11822	12625	4000	1000	28445	28262	28138	28579	28281
64004	28206	211	0	12	0	10	0	0	3	0	4983	28039	4	4	22375	5000	1000	4000	1000	4000	5000	21634	17	17055	27890	28288	3	10	5000	4000	9000	28281	28019	1	1	61001	1000	1000	4000	0	10	0	4002	0	0	0	4002	2	12	0	0	13860	10180	7211	3411	10	41	19183	3403	3801	7	54	44	28047	1000	14060	11968	12687	4000	1000	28242	28159	28218	28204	28184
64004	28425	212	1	17	1	13	1	0	4	0	4952	28057	4	4	21973	5000	1000	4000	1000	4000	5000	21629	18	17031	27785	28153	3	10	5000	4000	9000	28313	28074	1	1	61001	1000	1000	4004	5	12	2	4004	0	1	8	4000	4	14	4	0	14062	10070	7052	3363	5	40	19243	3352	3804	12	49	46	28006	1000	13917	12489	12818	4000	1000	28188	28023	28166	28523	28123
64004	28224	211	0	17	0	14	0	0	3	0	5229	28391	4	4	22318	5000	1000	4000	1000	4000	5000	21647	18	17037	27826	28346	3	10	5000	4000	9000	28047	28319	1	1	61001	1000	1000	4000	0	0	0	4000	0	0	2	4000	2	0	0	0	13844	10189	7040	3348	5	36	19287	3399	3804	8	53	49	27879	1000	14358	11689	13607	4000	1000	28316	28521	28216	28496	28403
64004	28235	212	1	13	1	16	1	0	4	0	5021	28470	0	0	22262	5000	1000	4000	1000	4000	5000	21614	18	17039	27948	28398	3	10	5000	4000	9000	28363	28159	1	1	61001	1000	1000	4004	5	0	1	4004	0	1	4	4000	4	0	4	2	13698	10248	7144	3355	7	43	19091	3378	3818	12	54	37	27929	1000	14116	12116	12885	4000	1000	28401	28305	28242	28366	28340
64004	28363	211	0	18	0	16	0	0	1	0	5023	28333	0	0	22060	5000	1000	4000	1000	4000	5000	21635	22	17036	28186	28038	3	10	5000	4000	9000	28151	28132	1	1	61001	1000	1000	4000	0	10	0	4000	0	0	0	4002	0	0	0	0	13484	10167	7082	3214	5	42	19355	3331	3813	8	52	42	27905	1000	14335	12010	12890	4000	1000	28664	28058	27948	28105	28184

Count: 8

Code:

  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	160057	1240	0	0	0	0	690	3	1	0	0	160027	16	0	0	25	400100	80100	320000	80100	320108	480499	7359352	160017	160042	160040	79978	3	80034	400100	200	320000	200	720000	160042	160040	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320000	0	0	5	320000	0	34	14	0	0	5110	1	17	1	1	160037	80000	320000	80100	160043	160043	160043	160043	160051
320204	160172	1241	0	0	0	0	0	0	1	0	0	160027	16	16	0	25	400100	80100	320000	80100	320000	400524	7359808	160017	160040	160042	79978	3	80118	400100	200	320000	200	720000	160040	160179	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320002	0	0	0	320000	2	0	0	0	0	5110	1	17	2	1	160037	80000	320000	80100	160043	160043	160043	160175	160041
320204	160042	1241	0	0	0	0	0	88	1	0	0	160025	16	16	0	25	400189	80100	320000	80100	320000	400524	7359424	160015	160050	160042	79980	3	80042	400237	200	320000	200	720000	160042	160040	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320002	0	0	787	320002	2	34	0	0	1	5110	2	17	1	1	160039	80000	320000	80100	160041	160041	160043	160043	160043
320204	160040	1240	0	0	0	0	12	0	0	0	0	160172	0	16	0	25	400100	80100	320000	80100	320108	400524	7359424	160015	160042	160040	79978	3	80024	400100	200	320000	200	720000	160040	160040	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320002	0	0	0	320002	2	0	0	0	0	5110	1	17	1	1	160047	80000	320000	80100	160041	160041	160041	160043	160188
320204	160042	1241	0	0	1	0	0	3	0	0	1	160027	16	16	0	25	400100	80100	320000	80100	320000	400524	7359424	160017	160050	160042	79980	3	80043	400100	200	320000	210	720810	160042	160040	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	1	0	5	320002	0	34	0	0	0	5110	1	62	1	1	160039	80000	320000	80100	160041	160041	160041	160041	160051
320204	160050	1241	0	0	0	0	21	3	0	0	1	160027	0	0	0	25	400100	80100	320000	80100	320000	480499	7364188	160017	160049	160042	79978	3	80032	400100	200	320000	200	720000	160040	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	0	0	320060	0	0	0	320000	2	0	0	0	0	5110	1	17	1	1	160039	80000	320000	80100	160050	160052	160041	160041	160043
320204	160042	1240	0	0	0	0	144	3	0	0	1	160025	0	0	0	25	400189	80100	320000	80100	320000	400524	7359808	160017	160042	160050	79980	3	80024	400100	200	320000	200	720000	160040	160042	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	3	0	745	320000	2	34	0	0	0	5110	2	17	1	1	160039	80000	320000	80100	160041	160174	160043	160041	160052
320204	160042	1242	0	0	0	0	24	9	0	0	1	160025	0	16	0	25	400100	80100	320000	80100	320000	400524	7364188	160015	160042	160051	79980	15	80040	400100	200	320000	200	720000	160040	160040	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	0	0	3	320000	2	34	0	0	0	5110	1	17	1	1	160156	80000	320000	80100	160320	160448	160323	160450	160439
320204	160576	1243	0	1	31	30	528	267	0	0	1	160549	16	0	512	846	402948	81088	321980	80131	320324	471730	7373812	160372	160436	160582	80287	33	80245	400648	200	320360	200	720810	160434	160307	4	1	80201	100	99	100	100	80000	80000	100	320000	0	36	0	0	320002	0	0	5	320000	0	34	0	0	0	5110	1	17	1	1	160048	80000	320000	80100	160041	160041	160043	160043	160041
320204	160042	1241	0	0	0	0	0	0	0	0	1	160027	0	0	0	25	400100	80100	320000	80100	320000	480499	7359352	160017	160051	160042	79978	3	80024	400100	200	320000	200	720000	160042	160050	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	0	0	320002	0	0	11	320002	2	34	0	0	0	5110	1	17	1	1	160037	80000	320000	80100	160043	160043	160043	160043	160051

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5e	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	160043	1240	0	0	1	0	1	0	3	0	0	0	160027	0	16	1	25	400010	80010	320000	80010	320000	480049	7364188	0	0	160015	160051	160042	79980	3	80024	400010	20	320000	20	720000	160043	160043	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	0	2	320000	0	0	2	320002	2	42	0	0	0	0	5020	1	17	1	2	160051	80000	320000	80010	160041	160044	160043	160041	160044
320024	160042	1240	0	0	0	1	0	12	3	0	0	0	160028	16	16	1	25	400010	80010	320000	80010	320000	400076	7359448	0	0	160021	160043	160042	79978	3	80024	400010	20	320000	20	720000	160042	160040	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	0	5	320002	2	42	0	0	0	0	5020	1	17	1	1	160040	80000	320000	80010	160043	160041	160043	160044	160044
320024	160042	1240	0	0	0	0	0	0	3	0	0	0	160025	16	16	0	25	400099	80010	320000	80010	320000	400076	7359448	0	0	160029	160042	160040	79981	3	80025	400010	20	320000	20	720000	160043	160181	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	0	0	320002	1	2	2	320002	2	42	0	0	0	0	5020	1	17	1	1	160039	80000	320000	80010	160041	160174	160043	160043	160043
320024	160042	1242	0	0	0	0	0	12	3	0	0	0	160028	16	0	1	25	400010	80010	320000	80010	320000	459110	7364284	0	0	160021	160043	160042	79980	3	80024	400010	20	320000	20	720000	160042	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	1	0	5	320000	2	42	0	0	0	0	5020	1	26	1	1	160040	80000	320000	80010	160043	160043	160043	160043	160043
320024	160040	1240	0	0	0	0	0	0	0	0	0	0	160027	16	16	1	25	400010	80039	320000	80010	320000	400076	7359448	0	0	160019	160042	160042	79983	3	80026	400147	20	320000	20	720000	160043	160042	2	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	0	2	320002	2	42	0	2	0	1	5032	1	17	1	1	160039	80000	320000	80010	160043	160179	160043	160044	160043
320024	160042	1241	0	0	0	0	0	12	3	0	0	0	160027	16	16	1	25	400010	80010	320000	80010	320000	400076	7359448	0	0	160015	160042	160042	79980	3	80025	400010	20	320000	20	720270	160042	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	0	0	320002	0	0	2	320002	2	42	0	0	0	0	5044	1	44	3	1	162067	80087	320000	80010	160176	160318	160583	160455	164587
320024	160300	1244	0	1	1	3	2	396	267	0	0	0	160161	16	16	73	25	400099	80010	320060	80039	320108	480049	7364188	0	0	160255	160454	160318	80212	36	80215	400421	20	320000	20	720000	160042	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320000	0	0	2	320002	2	42	0	0	0	0	5020	1	17	1	1	160039	80000	320000	80010	160043	160043	160122	160041	160043
320024	160042	1240	0	0	0	0	0	264	3	0	0	0	160025	16	0	0	25	400010	80010	320000	80010	320000	400076	7359448	0	0	160018	160042	160042	79978	3	80024	400010	20	320000	20	720000	160043	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	0	0	320002	0	0	5	320002	2	42	0	0	0	0	5020	1	17	1	1	160277	80000	320000	80010	160586	160046	160047	160043	160043
320024	160040	1241	0	0	0	0	0	0	3	0	0	0	160027	16	0	1	25	400010	80010	320000	80010	320000	400076	7364140	0	0	160015	160182	160043	79981	3	80027	400010	20	320000	20	720000	160040	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	44	0	0	320002	0	0	5	320002	2	42	0	0	0	0	5020	2	17	1	1	160039	80000	320000	80010	160044	160041	160043	160043	160043
320024	160042	1240	0	0	0	0	0	12	7	0	0	0	160027	16	16	0	25	400010	80010	320000	80010	320000	400076	7359448	0	0	160028	160040	160042	79981	3	80024	400010	20	320000	20	720000	160043	160042	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	0	0	320002	1	0	5	320002	2	42	0	0	0	0	5020	1	17	4	2	160039	80000	320000	80010	160043	160043	160043	160044	160055

ST1 (multiple, post-index, 4 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations