Firestorm: ST1 (multiple, post-index, 4 regs, 8H) measurements

Code:

  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	23	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
64005	29489	237	0	1	20	0	0	19	0	0	0	0	66	1	1	0	4654	29157	0	4	23286	5000	1000	4000	1000	4000	5000	21613	14	0	0	17005	28515	29438	3	10	5000	4000	9000	29146	29219	1	1	61001	1000	1000	4005	5	16	0	0	4004	0	1	4	4000	4	0	4	1	0	13213	9151	6880	3136	8	49	20276	3349	3795	13	49	48	28584	1000	16029	12945	14565	4000	1000	29340	29385	29380	29448	29405
64004	29411	235	0	0	15	0	0	18	0	0	0	0	84	1	0	0	4627	29118	4	4	23309	5000	1000	4000	1000	4000	5000	21604	22	0	0	17009	28522	29328	3	10	5000	4000	9000	29248	29214	1	1	61001	1000	1000	4000	0	0	0	0	4000	0	0	0	4000	0	12	0	0	0	13003	9322	6922	3070	10	47	20206	3340	3797	17	46	51	28611	1000	16097	12942	14668	4000	1000	29456	29376	29457	29481	29340
64004	29316	235	0	0	20	0	0	19	0	0	0	0	297	1	0	0	4656	29166	4	4	23258	5000	1000	4000	1000	4000	5000	21593	6	0	0	17021	28559	29389	3	10	5000	4000	9000	29226	29361	1	1	61001	1000	1000	4000	0	12	0	0	4000	0	0	0	4000	0	0	0	0	0	13144	9299	6858	3054	8	63	20370	3267	3801	18	50	53	28658	1000	16120	13003	14321	4000	1000	29256	29460	29383	29483	29481
64004	29323	235	0	0	14	0	0	15	0	0	0	0	363	1	0	0	4571	29152	4	4	23254	5000	1000	4000	1000	4000	5000	21610	10	0	0	17022	28663	29518	3	28	5000	4000	9000	29243	29287	1	1	61001	1000	1000	4000	0	12	0	0	4000	0	0	0	4000	0	12	0	0	0	13120	9454	6952	3118	3	48	20517	3318	3808	18	46	50	28679	1000	16432	12995	14502	4000	1000	29398	29388	29416	29321	29446
64004	29291	236	0	1	16	1	1	17	1	0	0	0	399	1	1	0	4636	29140	4	4	23297	5000	1000	4000	1000	4000	5000	21607	0	0	0	17045	28633	29495	3	10	5000	4000	9000	29313	29278	1	1	61001	1000	1000	4000	0	0	0	0	4000	0	0	0	4000	0	8	0	0	0	13190	9237	6890	3126	11	44	20393	3253	3807	22	46	46	28607	1000	16553	13186	14412	4000	1000	29423	29344	29310	29364	29428
64004	29299	237	0	0	18	0	0	17	0	0	0	0	369	1	1	0	4651	29112	0	0	23225	5000	1000	4000	1000	4000	5000	21607	5	0	0	17030	28558	29451	3	10	5000	4000	9000	29401	29243	1	1	61001	1000	1000	4000	0	8	0	0	4000	0	0	0	4000	0	0	0	0	0	13136	9526	6930	3126	9	46	20494	3285	3812	13	42	52	28602	1000	16012	13184	14715	4000	1000	29484	29349	29289	29301	29382
64004	29342	235	0	0	18	0	0	21	0	0	0	0	384	1	1	0	4613	29231	0	0	23347	5000	1000	4000	1000	4000	5000	21610	6	0	0	17026	28712	29475	3	10	5000	4000	9000	29273	29294	1	1	61001	1000	1000	4000	0	8	0	0	4000	0	0	0	4000	0	8	0	0	0	13209	9518	6913	3101	7	49	20426	3331	3816	17	45	44	28660	1000	16222	13139	14330	4000	1000	29377	29267	29369	29398	29430
64004	29425	236	0	0	19	0	0	20	0	0	0	0	348	1	0	0	4670	29301	0	0	23275	5000	1000	4000	1000	4000	5000	21610	0	0	0	17036	28652	29375	3	10	5000	4000	9000	29307	29317	1	1	61001	1000	1000	4000	0	8	0	0	4000	0	0	0	4000	0	0	0	0	0	13231	9466	6934	3174	3	44	20328	3251	3810	18	40	45	28610	1000	16359	12882	14504	4000	1000	29369	29383	29351	29361	29472
64004	29232	237	0	0	17	0	0	17	0	0	0	0	396	0	0	0	4788	29139	0	0	23557	5000	1000	4000	1000	4000	5000	21623	4	0	0	17066	28550	29468	3	85	5005	4000	9000	29276	29221	1	1	61001	1000	1000	4000	0	0	0	0	4000	0	0	0	4000	0	0	0	0	0	13071	9619	6973	3097	9	43	20276	3245	3810	12	45	44	28566	1000	15955	13075	14322	4000	1000	29442	29267	29294	29429	29486
64004	29498	238	0	1	19	0	1	16	1	0	0	0	66	5	0	0	4674	29175	0	0	23286	5000	1000	4000	1000	4000	5000	21615	5	0	8	17066	28796	29599	3	10	5000	4000	9000	29147	29271	1	1	61001	1000	1000	4006	6	0	0	0	4004	0	1	7	4000	4	12	4	0	0	13123	9345	6977	3155	7	46	20400	3272	3810	12	52	43	28606	1000	16222	13113	14230	4000	1000	29308	29504	29417	29374	29434

Count: 8

Code:

  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	160047	1240	1	0	1	1	0	0	0	20	1	0	0	1	160032	16	16	4	25	400100	80100	320000	80100	320000	400518	7360028	1	160022	0	160051	160064	79994	3	80036	400100	200	320000	200	720000	160054	160133	1	1	80201	100	99	100	100	80000	80000	100	320015	14	44	0	0	320016	1	1	22	320002	16	44	14	1	5110	1	17	1	1	160051	80000	320000	80100	160053	160053	160048	160054	160054
320204	160051	1241	1	0	0	0	0	0	45	20	0	0	0	1	160321	16	16	1	25	400100	80100	320000	80100	320108	400519	7359933	0	160027	0	160054	160054	79992	3	80036	400100	200	320000	200	720000	160047	160054	1	1	80201	100	99	100	100	80000	80000	100	320014	14	44	0	0	320016	1	1	27	320002	16	44	14	1	5110	1	17	1	1	160051	80000	320000	80100	160055	160135	160056	160055	160053
320204	160063	1241	1	1	1	0	1	0	0	14	0	0	0	1	160170	16	16	1	25	400100	80100	320000	80100	320108	400519	7359956	0	160029	0	160063	160054	79992	3	80045	400100	200	320000	200	720000	160054	160053	1	1	80201	100	99	100	100	80000	80000	100	320014	15	44	0	0	320018	1	0	24	320302	16	44	14	0	5110	1	26	1	1	160044	80000	320000	80100	160056	160048	160064	160065	160177
320204	160047	1241	1	0	1	0	0	0	0	18	0	0	0	1	160048	16	16	3	25	400100	80100	320000	80100	320000	400518	7360028	0	160111	0	160054	160052	80066	3	80036	400100	200	320000	200	720000	160051	160063	1	1	80201	100	99	100	100	80000	80000	100	320014	15	44	0	1	320016	0	1	16	320062	16	44	14	2	5110	1	17	1	1	160051	80000	320000	80100	160055	160057	160055	160055	160055
320204	160052	1241	1	1	2	0	0	0	0	19	0	0	1	1	160039	16	16	1	25	400100	80100	320000	80100	320000	400519	7360028	0	160029	0	160185	160054	79992	3	80034	400100	200	320000	200	720000	160054	160052	1	1	80201	100	99	100	100	80000	80000	100	320074	14	44	0	1	320016	0	0	804	320002	16	44	14	0	5110	1	17	1	1	160051	80000	320000	80100	160064	160053	160053	160053	160065
320204	160055	1240	1	0	2	0	0	0	0	19	0	0	0	1	160037	16	16	2	25	400100	80100	320060	80100	320000	400518	7359718	0	160027	0	160054	160186	79991	3	80037	400100	200	320000	200	720000	160051	160063	1	1	80201	100	99	100	100	80000	80000	100	320015	14	44	0	0	320014	6	1	16	320062	16	0	14	0	5110	1	17	1	1	160049	80000	320000	80100	160048	160055	160055	160048	160053
320204	160063	1241	1	2	1	0	0	0	0	18	0	0	0	1	160048	16	16	30	25	400100	80129	320000	80100	320000	400518	7360460	0	160027	0	160054	160052	79990	3	80037	400237	200	320000	200	720000	160055	160054	1	1	80201	100	99	100	100	80000	80000	100	320015	15	44	0	0	320016	1	0	16	320002	16	44	14	0	5110	1	17	1	1	160049	80029	320000	80100	160189	160048	160054	160053	160048
320204	160047	1241	1	0	1	1	0	0	0	18	0	0	0	1	160049	16	16	4	25	400100	80100	320000	80100	320000	400518	7360028	0	160039	0	160054	160052	79990	8	80029	400100	200	320000	200	720000	160052	160055	1	1	80201	100	99	100	100	80000	80000	100	320014	14	44	0	0	320016	0	1	14	320002	16	44	14	0	5110	1	17	1	1	160542	80029	320000	80100	160319	160187	160183	160320	160339
320204	160459	1243	1	0	2	0	3	9	540	285	0	0	0	1	160395	16	16	230	105	400278	80158	320780	80999	323132	475355	7499120	0	160422	0	160451	160330	80224	23	80226	400374	200	320240	200	720810	160325	160591	3	1	80201	100	99	100	100	80000	80000	100	320014	15	44	0	1	320016	0	1	19	320002	16	44	14	1	5110	1	17	1	1	160051	80000	320000	80100	160055	160055	160048	160055	160055
320204	160063	1241	1	0	0	1	0	0	12	18	0	0	0	1	160037	16	16	1	25	400189	80100	320000	80100	320000	400518	7359719	0	160029	0	160063	160054	79992	3	80037	400100	200	320000	200	720000	160054	160057	1	1	80201	100	99	100	100	80000	80000	100	320014	14	0	0	1	320016	1	1	22	320002	16	44	14	1	5110	1	16	1	1	160051	80000	320000	80100	160055	160055	160055	160055	160055

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	160052	1241	1	0	0	0	0	0	144	18	1	0	1	160032	0	16	4	25	400010	80010	320000	80010	320000	400068	7360028	0	0	0	160029	0	160054	160056	79997	3	80037	400147	20	320000	20	720000	160052	160055	2	1	80021	10	9	10	10	80000	80000	10	320014	15	44	0	0	320016	1	0	20	320002	16	44	14	1	0	5020	32	17	32	12	160049	80000	320000	80010	160055	160055	160188	160055	160052
320024	160054	1241	1	0	0	0	0	0	132	18	0	0	1	160038	0	0	3	25	400010	80010	320000	80010	320000	400069	7359908	0	0	0	160029	0	160052	160054	80001	10	80034	400010	20	320000	20	720000	160054	160052	1	1	80021	10	9	10	10	80000	80000	10	320014	14	44	0	1	320076	0	1	22	320002	16	44	14	0	0	5020	32	17	30	29	160051	80000	320000	80010	160056	160055	160064	160064	160055
320024	160052	1241	1	0	0	1	0	1	0	17	0	0	1	160172	16	16	148	83	400099	80793	320180	80097	320324	479421	7374392	0	0	0	160359	0	160583	160457	80303	45	80226	400558	20	324080	20	720540	160596	160464	4	1	80021	10	9	10	10	80000	80000	10	320197	14	44	59	3	320256	0	3	2338	320242	16	44	14	0	0	5056	28	44	25	28	160410	80116	320000	80010	160591	160457	160595	160458	160056
320024	160047	1199	1	1	0	1	0	0	0	19	0	0	1	160032	16	16	5	25	400010	80010	320000	80010	320000	400068	7360438	0	0	0	160029	0	160054	160054	79989	3	80036	400010	20	320000	20	720000	160054	160053	1	1	80021	10	9	10	10	80000	80000	10	320014	14	44	0	2	320016	1	0	14	320000	16	44	14	0	1	5020	30	17	12	32	160051	80000	320000	80010	160064	160055	160064	160064	160055
320024	160052	1241	1	1	0	1	0	0	0	18	0	0	1	160039	16	16	0	25	400010	80010	320000	80010	320000	400069	7359884	0	0	0	160029	0	160054	160055	79992	3	80037	400010	20	320000	20	720000	160054	160054	1	1	80021	10	9	10	10	80000	80000	10	320014	15	0	0	0	320016	0	0	18	320002	16	44	14	0	0	5020	29	17	34	30	160051	80000	320000	80010	160055	160055	160056	160055	160055
320024	160052	1241	1	1	0	1	0	0	12	19	0	0	1	160117	16	16	3	25	400010	80010	320000	80010	320000	400069	7359908	0	0	0	160022	0	160047	160054	79992	3	80029	400010	20	320000	20	720000	160054	160054	1	1	80021	10	9	10	10	80000	80000	10	320015	15	44	0	1	320016	0	0	18	320002	16	43	14	1	0	5020	34	17	29	27	160049	80000	320000	80010	160052	160053	160053	160055	160055
320024	160054	1241	1	1	0	0	0	0	12	17	0	0	1	160039	16	16	3	25	400010	80010	320000	80010	320000	400069	7359956	1	0	0	160029	0	160054	160054	79991	3	80036	400010	20	320000	20	720000	160054	160054	1	1	80021	10	9	10	10	80000	80000	10	320014	14	42	0	0	320016	0	0	16	320004	16	44	14	0	0	5020	31	17	31	31	160049	80000	320000	80010	160055	160054	160056	160055	160053
320024	160054	1241	1	0	0	0	0	0	0	19	0	0	1	160038	16	16	2	25	400010	80010	320000	80010	320000	400068	7360535	0	0	0	160030	3	160054	160052	80001	3	80034	400010	20	320000	20	720000	160054	160052	1	1	80021	10	9	10	10	80000	80000	10	320014	15	44	0	2	320016	1	1	19	320002	16	44	14	1	0	5020	31	17	12	32	160051	80000	320000	80010	160056	160055	160048	160055	160055
320024	160054	1240	1	0	0	0	0	0	0	22	0	0	1	160032	16	16	2	25	400010	80010	320000	80010	320000	400069	7360052	0	0	0	160029	0	160052	160055	79992	3	80036	400010	20	320000	20	720000	160052	160054	1	1	80021	10	9	10	10	80000	80000	10	320015	14	44	0	1	320016	0	0	16	320002	16	44	14	1	0	5020	26	17	26	29	160051	80000	320000	80010	160048	160055	160048	160057	160054
320024	160054	1241	1	0	0	1	0	0	12	17	0	0	1	160039	16	16	2	25	400010	80010	320000	80010	320000	400069	7360388	0	0	0	160029	0	160052	160054	79992	3	80037	400010	20	320000	20	720000	160052	160054	1	1	80021	10	9	10	10	80000	80000	10	320134	14	44	89	0	320196	0	8	2347	320122	16	44	14	0	0	5057	33	44	30	26	160410	80116	320000	80010	160456	160326	160593	160460	160316

ST1 (multiple, post-index, 4 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations