Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (single, H)

Test 1: uops

Code:

  st1 { v0.h }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e1f22233a3f464951schedule uop (52)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)f5f6f7f8fd
6200628388213123028102105034280691017312200010001000100010001090480001121737282862826531020001000100020001000281162823311610011000100010000201000000100000001378410192715234481358194603428381618626428025138051187812701100010002817928170282972814928398
620042842221302202300010522928061001711520001000100010001000109188000021773280822823831020001000100020001000283542805811610011000100010000201000000100002001390610347720535261057196233321381717566027856141771203313048100010002815128216282822817928030
62004281262120200170001052772839300172822000100010001000100010916800052174928233280533102000100010002000100028315283801161001100010001000020100000010001200138199962724133991165196343393381612596927855148381178312705100010002816328208283312796328220
620042841221202302200010521728152001714720001000100010001000109108000221778281772836631020001000100020001000281272798811610011000100010000201000000100102001394410325714332981257200103275381115575428051140081194812804100010002833628680283862841128282
620042846021202201902111050332811400176282000100010001000100010911800062181028138280793102000100010002000100028189284291161001100010001000000100000010000000138459879720634381355198173416381422585627915142711188812645100010002815328144282722834327984
620042835021401701700100515428098001721720001000100010001000109048000621771281802821431020001000100020001000281642836611610011000100010000201000000100000001404310458723034441553194923439381619615327974144661189213184100010002829428504280062841628336
620042827321101801700110513727966001723020001000100010001000109138000221806282322820731020001000100020001000283262813911610011000100010000001000200100003001409010601711232361055197233251381321586127978140531188212790100010002828828145281382833928103
620042821021202502000110498228081001716420001000100010001000109088000321750279592823231020001000100020001000282092824911610011000100010000201000000100002001365410251723233951160195413452381817615527921136211184112864100010002816628101282282814028386
620042838021001702200010526628105001722020001000100010001000109098000221787281342820831020001000100020001000280702812411610011000100010000001000201100002001420810039727234341357198693322381420555827877141751211012862100010002812328152282742822728190
620042822021202202000010512728120001719520001000100010001000109128000021803280292813031020001000100020001000283522807811610011000100010022001001011100012111380010205715533861058197223322381615605427924141091210813147100010002828728249282152810728191

Test 2: throughput

Count: 8

Code:

  st1 { v0.h }[1], [x6]
  st1 { v0.h }[1], [x6]
  st1 { v0.h }[1], [x6]
  st1 { v0.h }[1], [x6]
  st1 { v0.h }[1], [x6]
  st1 { v0.h }[1], [x6]
  st1 { v0.h }[1], [x6]
  st1 { v0.h }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f22233a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020640043322000000001923000400271600251601001008000080000100800008000050018397126400000400214004540042199590320001160100200800008000020016000080000400424004311802011009910010080000800001008000000008000210280002200005110616131340040080000800001004004340044400434004440044
16020440044322000000006331004002816160251601001008000080000100800008000050018397126400001400214004340042199590320001160100200800008000020016000080000400434004311802011009910010080000800001008000004200800020028000224200051101316151240039080000800001004004340044400434004440043
16020440043321000000004540004002716160251601001008000080000100800008000050018397126400000400214004340043199600320000160100200800008000020016000080000400424004311802011009910010080000800001008000004200800020028000224200051101316121240040080000800001004004440044400454004440044
16020440043322000000000300040028161602516010010080000800001008000080000500183971264000004002140043400441995903200011601002008000080000200160000800004004340042118020110099100100800008000010080000042008006212680002242001511071611840040080000800001004004540043400444004440044
160204400423220000000003000400271600251601001008000080000100800008000050018397126400000400214004540043199590320001160100200800008000020016000080000400434004311802011009910010080000800001008000004200800020008000224200051101416131340040080000800001004004440043400444004340044
16020440043321000000000300040028161602516010010080000800001008000080000500183971264000004002140042400421995903200011601002008000080000200160000800004004240043118020110099100100800008000010080000000080002002800022420005110101691040040080000800001004004440043400444004440043
1602044004232200000000123000400300160251601001008000080000100800008000050018397126400000400214004240046199590320000160100200800008000020016000080000400424004311802011009910010080000800001008000004200800020028000024200051101116131040040080000800001004004440043400434004340043
160204400423210000000018400040027161602516010010080000800001008000080108500183971264000004002140043400471995903200011601002008000080000200160000800004004340248118020110099100100800008000010080000000080002002800622420005110131661440039080000800001004004440043400444004440044
16020440043322000000001503000400281616025160100100800008000010080000800005001839712640000040021400424004819959032000116010020080000800002001600008000040043400421180201100991001008000080000100800000440080000002800022420005110816151340040080000800001004004440044400444004440044
1602044004332200000000030004002816002516010010080000800001008000080000500183971264000004002140043400471995903200011601002008000080000200160000800004004340043118020110099100100800008000010080000042008000200280002242000511081612840040080000800001004004440044400444004340043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03mmu table walk instruction (07)1e1f233f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d cache miss st (a2)a4st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160026400423190030400281616025160010108000080000108000080000501839712640000040021400434004319982320023160010208000080000201600008000040043400421180021109101080000800001080000008000200280002042502051654400398000080000104004340044400434004440044
160024400433100600400281616025160010108000080000108000080000501839712640000040021400424005419982320023160010208000080000201600008000040043400421180021109101080000800001080000420800020038000220502031633400408000080000104004440045400444004440044
1600244004331100304002716160251600101080000800001080000800005018397126400000400214004440042199823200231600102080000800002016000080000400434004311800211091010800008000010800004408000210880002242502041634400408000080000104004440044400444004340044
1600244004231000304002816160251600101080000800001080000800005018397126400000400284028440499199828200231600102080000800002016000080000400434004211800211091010800008000010800004208000200880002242502041644400408000080000104004740048400474004440044
1600244004230000404002716160251600101080000800001080000800005018397126400000400214004340043199893200231600102080000800002016000080000400434004311800211091010800008000010800004208000200280002242503141633400408000080000104004340044400434004440044
16002440044310003040027000251600101080000800001080000800005018397126400000400214005340042199823200231600102080000800002016000080000400434004311800211091010800008000010800004208000210380002242502041644400408000080000104004440044400444004440044
160024400432990600400281616025160010108000080000108000080000501839712640000040021400434004319982320023160010208000080000201600008000040044400421180021109101080000800001080000420800000028000220502041643400398000080000104004340043400434004440044
1600244004330000304002716160251600101080000800001080000800005018397126400000400214004340043199823200231600102080000800002016000080000400434004311800211091010800008000010800004208000200580002242502031633400408000080000104004440044400444004540044
1600244004230000004023916160251600101080000800001080000800005018397126400000400214004240043199823200231600102080000800002016000080000400424004311800211091010800008000010800004208000200080002242502031633400408000080000104004440044400444004340043
1600244004329900304002816160251600101080000800001080000800005018397126400000400214004340043199823200221600102080000800002016000080000400434004311800211091010800008000010800004208000200580002242502041634400408000080000104004440044400444004440044