Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st1 { v0.b }[1], [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 3.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
62006 | 28963 | 234 | 1 | 24 | 0 | 0 | 27 | 1 | 0 | 0 | 39 | 2 | 1 | 0 | 4724 | 28878 | 1 | 0 | 17855 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10906 | 8000 | 0 | 21789 | 28617 | 28909 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 28965 | 29029 | 1 | 1 | 61001 | 1000 | 1000 | 1001 | 1 | 3 | 1 | 1002 | 1 | 0 | 1 | 1000 | 1 | 4 | 1 | 1 | 0 | 13108 | 9177 | 6902 | 3112 | 5 | 46 | 20257 | 3241 | 3819 | 31 | 46 | 45 | 28238 | 1000 | 15697 | 12909 | 13865 | 1000 | 1000 | 1000 | 28997 | 28936 | 28782 | 28977 | 28781 |
62004 | 28947 | 232 | 1 | 17 | 1 | 0 | 18 | 1 | 0 | 0 | 363 | 2 | 1 | 0 | 4687 | 28796 | 0 | 0 | 18111 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10907 | 8000 | 6 | 21762 | 28760 | 28927 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 28797 | 28811 | 1 | 1 | 61001 | 1000 | 1000 | 1004 | 1 | 2 | 9 | 1001 | 0 | 1 | 1 | 1000 | 1 | 2 | 1 | 2 | 0 | 13092 | 9322 | 7003 | 3165 | 9 | 45 | 20140 | 3338 | 3819 | 26 | 49 | 53 | 28422 | 1000 | 15221 | 12874 | 14291 | 1000 | 1000 | 1000 | 29108 | 28954 | 29055 | 29108 | 28852 |
62004 | 28812 | 231 | 1 | 18 | 1 | 1 | 20 | 1 | 0 | 0 | 45 | 89 | 0 | 0 | 4720 | 28718 | 0 | 0 | 17859 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10903 | 8000 | 0 | 21691 | 28567 | 28783 | 8 | 28 | 3003 | 1000 | 1000 | 3000 | 1000 | 28749 | 28811 | 1 | 1 | 61001 | 1000 | 1000 | 1001 | 2 | 0 | 1 | 1001 | 0 | 1 | 1 | 1000 | 1 | 2 | 1 | 0 | 0 | 13276 | 9556 | 6902 | 3177 | 13 | 47 | 20351 | 3260 | 3817 | 25 | 48 | 45 | 28356 | 1000 | 16029 | 12651 | 13831 | 1000 | 1000 | 1000 | 28772 | 28947 | 28855 | 28917 | 28860 |
62004 | 28823 | 232 | 1 | 15 | 1 | 2 | 14 | 0 | 0 | 0 | 30 | 2 | 0 | 0 | 4613 | 28652 | 0 | 0 | 17959 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10904 | 8000 | 0 | 21733 | 28762 | 29042 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 28711 | 28863 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 1 | 2 | 0 | 1001 | 1 | 1 | 1 | 1000 | 1 | 0 | 1 | 1 | 0 | 13050 | 9518 | 6989 | 3092 | 5 | 47 | 20234 | 3207 | 3817 | 18 | 44 | 46 | 28397 | 1000 | 15536 | 13066 | 13928 | 1000 | 1000 | 1000 | 28831 | 28924 | 28956 | 28914 | 29110 |
62004 | 29064 | 232 | 1 | 22 | 1 | 1 | 22 | 1 | 0 | 0 | 57 | 2 | 0 | 0 | 4723 | 28587 | 0 | 0 | 18050 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10905 | 8008 | 2 | 21770 | 28838 | 29295 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 29115 | 29075 | 1 | 1 | 61001 | 1000 | 1000 | 1004 | 2 | 2 | 1 | 1001 | 0 | 0 | 4 | 1000 | 1 | 2 | 1 | 1 | 0 | 13112 | 9333 | 6844 | 3085 | 14 | 51 | 20536 | 3178 | 3815 | 26 | 48 | 55 | 28521 | 1000 | 16150 | 13213 | 14487 | 1000 | 1000 | 1000 | 29167 | 29211 | 29118 | 29228 | 29097 |
62004 | 29154 | 234 | 1 | 20 | 1 | 0 | 19 | 1 | 0 | 0 | 33 | 2 | 0 | 0 | 4709 | 28967 | 0 | 0 | 18315 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10908 | 8000 | 6 | 21695 | 28948 | 29258 | 3 | 10 | 3000 | 1000 | 1000 | 3003 | 1000 | 29151 | 29421 | 3 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 2 | 2 | 1001 | 1 | 2 | 4 | 1000 | 1 | 2 | 1 | 1 | 0 | 13027 | 9321 | 6865 | 3097 | 13 | 45 | 20341 | 3216 | 3808 | 24 | 41 | 47 | 28464 | 1000 | 15884 | 12755 | 14170 | 1000 | 1000 | 1000 | 29154 | 29049 | 29106 | 28969 | 29030 |
62004 | 29005 | 234 | 1 | 19 | 0 | 0 | 17 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 4612 | 28798 | 0 | 0 | 18051 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10906 | 8000 | 4 | 21741 | 28775 | 29057 | 8 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 28806 | 29001 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 2 | 2 | 1001 | 1 | 1 | 1 | 1000 | 1 | 0 | 1 | 1 | 0 | 13200 | 9250 | 6928 | 3093 | 7 | 50 | 20432 | 3225 | 3816 | 22 | 47 | 54 | 28533 | 1000 | 15780 | 12894 | 14168 | 1000 | 1000 | 1000 | 29046 | 29186 | 28982 | 28979 | 29018 |
62004 | 28950 | 233 | 1 | 19 | 0 | 1 | 20 | 0 | 0 | 0 | 0 | 89 | 0 | 0 | 4649 | 28821 | 0 | 0 | 18047 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10897 | 8000 | 7 | 21705 | 28780 | 29096 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 28908 | 28981 | 1 | 1 | 61001 | 1000 | 1000 | 1005 | 2 | 0 | 2 | 1001 | 0 | 1 | 1 | 1000 | 1 | 2 | 1 | 1 | 0 | 13177 | 9234 | 6868 | 3092 | 9 | 49 | 20368 | 3216 | 3810 | 25 | 46 | 48 | 28520 | 1000 | 16022 | 12922 | 13994 | 1000 | 1000 | 1000 | 28985 | 29110 | 29031 | 29061 | 28979 |
62004 | 29133 | 233 | 1 | 21 | 1 | 2 | 22 | 1 | 0 | 0 | 33 | 2 | 0 | 0 | 4606 | 28845 | 0 | 1 | 17946 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10900 | 8000 | 0 | 21711 | 28768 | 28937 | 3 | 10 | 3003 | 1000 | 1000 | 3000 | 1000 | 28934 | 28982 | 1 | 1 | 61001 | 1000 | 1000 | 1003 | 2 | 0 | 5 | 1001 | 0 | 1 | 1 | 1002 | 2 | 2 | 1 | 3 | 0 | 13049 | 9173 | 6939 | 3101 | 10 | 49 | 20416 | 3296 | 3817 | 17 | 49 | 49 | 28472 | 1000 | 15841 | 12912 | 13928 | 1000 | 1000 | 1000 | 29049 | 29095 | 28989 | 29118 | 28941 |
62004 | 28951 | 233 | 1 | 15 | 2 | 1 | 18 | 1 | 0 | 0 | 0 | 90 | 0 | 1 | 4716 | 28817 | 0 | 1 | 17894 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10897 | 8000 | 0 | 21701 | 28725 | 28987 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 28979 | 28956 | 2 | 1 | 61001 | 1000 | 1000 | 1005 | 3 | 0 | 1 | 1001 | 0 | 3 | 1 | 1001 | 1 | 2 | 1 | 1 | 0 | 13043 | 9272 | 6931 | 3076 | 13 | 45 | 20320 | 3208 | 3811 | 19 | 44 | 47 | 28505 | 1000 | 15813 | 12695 | 14054 | 1000 | 1000 | 1000 | 28973 | 28967 | 28960 | 29120 | 28961 |
Count: 8
Code:
st1 { v0.b }[1], [x6], x8 st1 { v0.b }[1], [x6], x8 st1 { v0.b }[1], [x6], x8 st1 { v0.b }[1], [x6], x8 st1 { v0.b }[1], [x6], x8 st1 { v0.b }[1], [x6], x8 st1 { v0.b }[1], [x6], x8 st1 { v0.b }[1], [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 23 | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5e | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cf | d5 | map dispatch bubble (d6) | da | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 80040 | 620 | 0 | 0 | 0 | 0 | 285 | 4 | 0 | 80025 | 8 | 8 | 3 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 1 | 1 | 80001 | 1 | 21 | 0 | 5110 | 12 | 16 | 0 | 12 | 13 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 33 | 4 | 0 | 80025 | 8 | 8 | 0 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80000 | 0 | 4 | 80001 | 1 | 0 | 0 | 5110 | 12 | 16 | 0 | 14 | 14 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 30 | 4 | 0 | 80025 | 8 | 8 | 0 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 3 | 80001 | 1 | 21 | 0 | 5110 | 12 | 16 | 0 | 12 | 12 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 9 | 2 | 0 | 80025 | 8 | 8 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 3 | 80001 | 1 | 24 | 0 | 5110 | 11 | 16 | 0 | 12 | 12 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 80025 | 8 | 8 | 3 | 25 | 240100 | 80100 | 80120 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 1 | 9 | 80001 | 1 | 21 | 0 | 5110 | 12 | 16 | 0 | 13 | 13 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 80025 | 8 | 8 | 0 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359010 | 3758848 | 640000 | 0 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 3 | 80000 | 1 | 21 | 0 | 5110 | 16 | 16 | 0 | 10 | 13 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 12 | 2 | 0 | 80025 | 8 | 8 | 0 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 23 | 0 | 0 | 80001 | 0 | 3 | 80001 | 1 | 21 | 0 | 5110 | 12 | 16 | 0 | 12 | 13 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 80025 | 8 | 8 | 0 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 3 | 80001 | 0 | 21 | 0 | 5110 | 14 | 16 | 0 | 13 | 13 | 80501 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 345 | 2 | 0 | 80025 | 8 | 8 | 3 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80128 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 3 | 80001 | 1 | 22 | 0 | 5110 | 12 | 16 | 0 | 8 | 12 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 9 | 4 | 0 | 80025 | 8 | 0 | 3 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 2 | 21 | 0 | 0 | 80001 | 0 | 3 | 80001 | 1 | 21 | 0 | 5110 | 13 | 16 | 0 | 14 | 13 | 80037 | 80092 | 80000 | 80000 | 80100 | 80041 | 80180 | 80041 | 80041 | 80041 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 0e | 18 | 19 | 1e | 1f | 22 | 23 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | 91 | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cf | d0 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 80040 | 620 | 0 | 0 | 0 | 0 | 636 | 0 | 1 | 0 | 1 | 80025 | 8 | 8 | 1 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 0 | 0 | 5022 | 0 | 4 | 16 | 3 | 5 | 80037 | 80726 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 0 | 0 | 0 | 0 | 945 | 0 | 1 | 0 | 1 | 80025 | 8 | 8 | 2 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 1 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 5 | 80001 | 1 | 0 | 0 | 5022 | 0 | 5 | 16 | 4 | 5 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 504 | 3 | 1 | 0 | 1 | 80025 | 8 | 8 | 0 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 5022 | 0 | 4 | 16 | 5 | 4 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80163 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 0 | 0 | 0 | 0 | 954 | 2 | 1 | 0 | 1 | 80025 | 8 | 8 | 3 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 4 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80000 | 0 | 17 | 0 | 5022 | 0 | 3 | 16 | 5 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 486 | 2 | 1 | 0 | 1 | 80025 | 8 | 8 | 0 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 2 | 0 | 6 | 80000 | 1 | 17 | 0 | 5022 | 0 | 5 | 16 | 4 | 5 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 12 | 3 | 0 | 0 | 1 | 80025 | 8 | 8 | 3 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 1 | 80000 | 1 | 18 | 0 | 5022 | 0 | 5 | 16 | 3 | 4 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 963 | 6 | 0 | 0 | 1 | 80025 | 8 | 8 | 3 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80108 | 4358429 | 3758848 | 640000 | 1 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 1 | 0 | 2 | 80001 | 1 | 17 | 0 | 5022 | 0 | 5 | 16 | 5 | 5 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 0 | 0 | 0 | 0 | 306 | 0 | 0 | 0 | 1 | 80025 | 8 | 8 | 3 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 1 | 0 | 5 | 80001 | 1 | 17 | 0 | 5022 | 0 | 4 | 16 | 5 | 4 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 0 | 0 | 0 | 0 | 6 | 3 | 0 | 0 | 1 | 80025 | 8 | 8 | 3 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 1 | 80001 | 1 | 17 | 0 | 5022 | 0 | 5 | 16 | 4 | 5 | 80037 | 81736 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80162 | 620 | 0 | 0 | 0 | 0 | 342 | 0 | 1 | 0 | 1 | 80025 | 0 | 8 | 1 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80000 | 0 | 17 | 7 | 5022 | 0 | 5 | 16 | 5 | 5 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |