Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st1 { v0.d }[1], [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 3.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
62006 | 29320 | 229 | 1 | 9 | 1 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 4477 | 29348 | 1 | 0 | 18315 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10907 | 8000 | 9 | 21709 | 28948 | 29380 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 29380 | 29394 | 1 | 1 | 61001 | 1000 | 1000 | 1004 | 1 | 4 | 1 | 1001 | 0 | 0 | 1 | 1000 | 1 | 3 | 0 | 0 | 0 | 13079 | 9311 | 6892 | 3074 | 6 | 51 | 20856 | 3188 | 3812 | 19 | 43 | 46 | 28577 | 1000 | 16288 | 13480 | 14609 | 1000 | 1000 | 1000 | 29460 | 29334 | 29459 | 29348 | 29271 |
62004 | 29286 | 228 | 0 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | 0 | 1 | 0 | 4585 | 29106 | 0 | 1 | 18486 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10908 | 8000 | 10 | 21723 | 28964 | 29472 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 29311 | 29207 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 3 | 2 | 1001 | 0 | 1 | 1 | 1000 | 1 | 4 | 1 | 1 | 0 | 13171 | 9312 | 6960 | 3105 | 5 | 43 | 20698 | 3224 | 3819 | 16 | 46 | 46 | 28650 | 1000 | 16297 | 13332 | 14268 | 1000 | 1000 | 1000 | 29258 | 29203 | 29196 | 29351 | 29344 |
62004 | 29356 | 226 | 1 | 10 | 1 | 1 | 10 | 1 | 0 | 0 | 0 | 1 | 0 | 4667 | 28988 | 0 | 0 | 18291 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10903 | 8000 | 8 | 21725 | 28906 | 29416 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 29223 | 29315 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 1 | 0 | 1 | 1001 | 0 | 1 | 1 | 1000 | 1 | 3 | 0 | 0 | 0 | 13136 | 9336 | 6990 | 3066 | 6 | 51 | 20726 | 3164 | 3814 | 18 | 48 | 43 | 28568 | 1000 | 15873 | 13362 | 14560 | 1000 | 1000 | 1000 | 29229 | 29294 | 29294 | 29385 | 29293 |
62004 | 29346 | 227 | 1 | 9 | 1 | 0 | 13 | 1 | 0 | 0 | 0 | 1 | 0 | 4663 | 29128 | 0 | 0 | 18308 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10909 | 8000 | 6 | 21683 | 28967 | 29398 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 29294 | 29289 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 1 | 4 | 1 | 1001 | 0 | 1 | 1 | 1000 | 0 | 3 | 1 | 0 | 0 | 12971 | 9249 | 6848 | 3100 | 4 | 44 | 20701 | 3107 | 3813 | 22 | 44 | 42 | 28574 | 1000 | 16147 | 13211 | 14576 | 1000 | 1000 | 1000 | 29277 | 29274 | 29319 | 29192 | 29271 |
62004 | 29284 | 228 | 0 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 4516 | 29140 | 0 | 0 | 18326 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10899 | 8000 | 9 | 21719 | 28961 | 29340 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 29193 | 29326 | 1 | 1 | 61001 | 1000 | 1000 | 1003 | 1 | 0 | 0 | 1001 | 0 | 1 | 1 | 1000 | 1 | 3 | 0 | 0 | 0 | 12943 | 9164 | 6866 | 3118 | 5 | 49 | 20690 | 3262 | 3817 | 18 | 45 | 46 | 28577 | 1000 | 16206 | 13404 | 14621 | 1000 | 1000 | 1000 | 29248 | 29419 | 29339 | 29384 | 29264 |
62004 | 29406 | 227 | 0 | 8 | 0 | 0 | 9 | 0 | 0 | 0 | 24 | 0 | 0 | 4467 | 29203 | 0 | 0 | 18317 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10907 | 8000 | 11 | 21681 | 28945 | 29344 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 29281 | 29303 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 0 | 0 | 1001 | 0 | 0 | 4 | 1000 | 0 | 0 | 1 | 0 | 0 | 12988 | 9138 | 6852 | 3162 | 6 | 47 | 20681 | 3182 | 3813 | 23 | 49 | 45 | 28620 | 1000 | 16413 | 13440 | 14520 | 1000 | 1000 | 1000 | 29359 | 29333 | 29352 | 29387 | 29334 |
62004 | 29341 | 227 | 1 | 8 | 0 | 1 | 8 | 1 | 0 | 0 | 0 | 1 | 0 | 4598 | 29105 | 0 | 0 | 18297 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10904 | 8000 | 12 | 21760 | 28998 | 29386 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 29248 | 29194 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 3 | 1 | 1001 | 1 | 1 | 1 | 1000 | 1 | 0 | 0 | 0 | 0 | 13172 | 9163 | 6907 | 3134 | 3 | 50 | 20687 | 3228 | 3820 | 15 | 52 | 45 | 28516 | 1000 | 16486 | 13333 | 14665 | 1000 | 1000 | 1000 | 29249 | 29477 | 29339 | 29435 | 29379 |
62004 | 29272 | 227 | 0 | 13 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | 1 | 0 | 4728 | 29189 | 1 | 0 | 18372 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10907 | 8000 | 10 | 21719 | 29033 | 29235 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 29208 | 29284 | 1 | 1 | 61001 | 1000 | 1000 | 1003 | 3 | 3 | 0 | 1001 | 0 | 0 | 1 | 1000 | 1 | 3 | 1 | 1 | 0 | 13100 | 9511 | 6905 | 3113 | 3 | 46 | 20791 | 3254 | 3819 | 21 | 43 | 42 | 28554 | 1000 | 16370 | 13382 | 14510 | 1000 | 1000 | 1000 | 29242 | 29307 | 29328 | 29331 | 29307 |
62004 | 29333 | 227 | 0 | 8 | 1 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 4700 | 29139 | 0 | 0 | 18376 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10902 | 8000 | 7 | 21645 | 29063 | 29294 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 29336 | 29244 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 1 | 3 | 1 | 1001 | 0 | 1 | 4 | 1000 | 1 | 0 | 0 | 0 | 0 | 13128 | 9490 | 6826 | 3154 | 3 | 46 | 20743 | 3177 | 3818 | 13 | 45 | 41 | 28541 | 1000 | 16092 | 13260 | 14617 | 1000 | 1000 | 1000 | 29317 | 29376 | 29435 | 29230 | 29251 |
62004 | 29340 | 228 | 0 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 4549 | 29086 | 1 | 1 | 18263 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10907 | 8000 | 11 | 21657 | 28934 | 29342 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 29173 | 29211 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 3 | 1 | 1001 | 0 | 1 | 4 | 1000 | 0 | 3 | 1 | 0 | 0 | 13240 | 9437 | 6895 | 3063 | 6 | 48 | 20837 | 3137 | 3822 | 19 | 42 | 44 | 28512 | 1002 | 16380 | 13366 | 14311 | 1000 | 1000 | 1000 | 29239 | 29332 | 29336 | 29359 | 29235 |
Count: 8
Code:
st1 { v0.d }[1], [x6], x8 st1 { v0.d }[1], [x6], x8 st1 { v0.d }[1], [x6], x8 st1 { v0.d }[1], [x6], x8 st1 { v0.d }[1], [x6], x8 st1 { v0.d }[1], [x6], x8 st1 { v0.d }[1], [x6], x8 st1 { v0.d }[1], [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 3 | 0 | 0 | 0 | 80025 | 0 | 8 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 1 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 2 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 2 | 0 | 0 | 0 | 80025 | 8 | 8 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 1 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 4 | 80001 | 1 | 17 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 80152 | 8 | 8 | 0 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 5 | 80001 | 1 | 17 | 0 | 0 | 0 | 0 | 0 | 5110 | 2 | 16 | 1 | 2 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 80025 | 8 | 0 | 294 | 25 | 240639 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 1 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80120 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 1 | 80061 | 1 | 17 | 0 | 0 | 0 | 0 | 0 | 5110 | 2 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 80025 | 8 | 8 | 3 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 0 | 0 | 0 | 80000 | 1 | 0 | 2 | 80001 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 132 | 0 | 1 | 0 | 0 | 80025 | 8 | 8 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 1 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80120 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 19 | 0 | 0 | 80001 | 1 | 0 | 1 | 80001 | 1 | 17 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 2 | 1 | 80142 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 80025 | 8 | 8 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 1 | 0 | 1 | 80001 | 1 | 17 | 0 | 0 | 0 | 0 | 0 | 5110 | 2 | 16 | 1 | 2 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 132 | 2 | 0 | 0 | 0 | 80025 | 8 | 0 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 25 | 7 | 1 | 0 | 0 | 0 | 5110 | 2 | 16 | 1 | 2 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80162 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 9 | 0 | 0 | 1 | 80025 | 11 | 11 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4361393 | 3758848 | 640000 | 1 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80067 | 8 | 25 | 0 | 0 | 80008 | 0 | 1 | 14 | 80001 | 8 | 25 | 7 | 1 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 2 | 80037 | 80090 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80164 | 620 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 80025 | 8 | 8 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 2 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80164 | 80041 | 80041 | 80041 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 57 | 3 | 1 | 0 | 0 | 80025 | 0 | 8 | 3 | 53 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80108 | 4358429 | 3758848 | 640000 | 80015 | 80162 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 0 | 5040 | 0 | 3 | 16 | 3 | 5 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 312 | 2 | 0 | 0 | 0 | 80025 | 8 | 8 | 3 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240350 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80000 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 0 | 5020 | 0 | 4 | 16 | 5 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80164 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 471 | 3 | 0 | 0 | 0 | 80025 | 0 | 8 | 2 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 0 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 0 | 5020 | 0 | 3 | 16 | 5 | 4 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80161 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 357 | 3 | 0 | 0 | 0 | 80025 | 8 | 0 | 3 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4360828 | 3758848 | 640000 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80000 | 0 | 0 | 1 | 80001 | 1 | 17 | 0 | 2 | 5020 | 752 | 4 | 16 | 4 | 4 | 80141 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80161 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 1 | 80025 | 0 | 0 | 1 | 25 | 240010 | 80100 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 640000 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80120 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 7 | 29 | 0 | 0 | 80008 | 0 | 0 | 11 | 80061 | 1 | 21 | 0 | 0 | 5020 | 0 | 6 | 16 | 5 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 21 | 12 | 0 | 0 | 1 | 80025 | 8 | 8 | 2 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240350 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 21 | 0 | 2 | 80001 | 1 | 0 | 11 | 80001 | 0 | 21 | 0 | 0 | 5020 | 0 | 3 | 16 | 3 | 4 | 80037 | 80092 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 27 | 2 | 0 | 0 | 0 | 80025 | 0 | 0 | 3 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 640000 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80067 | 8 | 29 | 0 | 0 | 80008 | 0 | 0 | 1 | 80001 | 8 | 21 | 0 | 0 | 5020 | 0 | 4 | 16 | 5 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 252 | 9 | 0 | 0 | 0 | 80147 | 9 | 0 | 2 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 0 | 0 | 0 | 80008 | 0 | 0 | 11 | 80061 | 8 | 29 | 7 | 1 | 5020 | 0 | 3 | 16 | 4 | 4 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 21 | 97 | 0 | 0 | 1 | 80025 | 8 | 8 | 5 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 640000 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 9 | 21 | 0 | 0 | 80061 | 0 | 0 | 1 | 80001 | 1 | 21 | 0 | 0 | 5020 | 0 | 5 | 16 | 3 | 2 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 9 | 0 | 0 | 0 | 0 | 80025 | 0 | 0 | 1 | 25 | 240010 | 80010 | 80000 | 80060 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 640000 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80120 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 0 | 0 | 0 | 80008 | 0 | 0 | 6 | 80001 | 8 | 29 | 7 | 0 | 5020 | 0 | 3 | 16 | 3 | 5 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |