Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st1 { v0.h }[1], [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 3.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5e | 5f | 60 | 61 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | l1d cache miss st nonspec (c0) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
62006 | 29020 | 232 | 22 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4675 | 28699 | 1 | 1 | 17899 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10902 | 8000 | 0 | 11 | 1 | 9 | 21828 | 28691 | 28872 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 28954 | 28835 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 0 | 4 | 0 | 1000 | 0 | 4 | 0 | 13181 | 9346 | 6859 | 3148 | 12 | 54 | 20504 | 3209 | 3812 | 18 | 63 | 58 | 28356 | 1000 | 15862 | 12797 | 14019 | 1000 | 1000 | 1000 | 28924 | 28834 | 28833 | 28956 | 29030 |
62004 | 28851 | 233 | 25 | 0 | 0 | 22 | 0 | 0 | 0 | 132 | 1 | 0 | 0 | 4672 | 28740 | 1 | 0 | 17918 | 3000 | 1000 | 1000 | 1000 | 1000 | 1001 | 1000 | 5000 | 10904 | 8000 | 0 | 7 | 0 | 0 | 21756 | 28620 | 28921 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 28787 | 28888 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 3 | 0 | 0 | 13183 | 9335 | 6820 | 3082 | 12 | 58 | 20286 | 3275 | 3811 | 17 | 61 | 58 | 28401 | 1000 | 15809 | 12831 | 14040 | 1000 | 1000 | 1000 | 28978 | 28867 | 28892 | 29039 | 28915 |
62004 | 28980 | 232 | 18 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 88 | 0 | 0 | 4644 | 28640 | 0 | 1 | 17790 | 3006 | 1000 | 1000 | 1000 | 1000 | 1001 | 1000 | 5000 | 10913 | 8000 | 0 | 11 | 0 | 8 | 21682 | 28612 | 28871 | 3 | 47 | 3000 | 1000 | 1000 | 3000 | 1000 | 28760 | 28794 | 2 | 1 | 61001 | 1000 | 1000 | 1002 | 0 | 0 | 3 | 1002 | 0 | 0 | 0 | 1002 | 0 | 4 | 0 | 12922 | 9367 | 6862 | 3148 | 6 | 57 | 20305 | 3146 | 3812 | 16 | 65 | 61 | 28332 | 1001 | 15714 | 12986 | 14054 | 1000 | 1000 | 1000 | 29068 | 29189 | 29048 | 29626 | 29550 |
62004 | 29562 | 240 | 25 | 1 | 1 | 16 | 0 | 5 | 4 | 528 | 529 | 0 | 0 | 4430 | 28904 | 0 | 1 | 17830 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10909 | 8000 | 0 | 7 | 1 | 0 | 21694 | 28490 | 28721 | 9 | 10 | 3000 | 1000 | 1000 | 3000 | 1001 | 28708 | 28702 | 2 | 1 | 61001 | 1000 | 1000 | 1004 | 0 | 3 | 0 | 1000 | 0 | 2 | 25 | 1000 | 3 | 0 | 0 | 13142 | 9337 | 6974 | 3156 | 12 | 49 | 20074 | 3193 | 3808 | 25 | 59 | 63 | 28157 | 1000 | 15204 | 12681 | 13962 | 1000 | 1000 | 1000 | 29139 | 29034 | 29043 | 28892 | 29004 |
62004 | 28875 | 234 | 27 | 1 | 0 | 22 | 0 | 0 | 0 | 132 | 1 | 0 | 0 | 4793 | 28757 | 0 | 0 | 17593 | 3000 | 1001 | 1001 | 1000 | 1001 | 1000 | 1000 | 5000 | 10901 | 8000 | 0 | 3 | 0 | 0 | 21702 | 28480 | 28776 | 7 | 10 | 3003 | 1000 | 1001 | 3000 | 1001 | 28806 | 28871 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 2 | 0 | 0 | 1000 | 1 | 0 | 485 | 1000 | 2 | 0 | 0 | 13237 | 9542 | 6877 | 3131 | 8 | 59 | 20225 | 3225 | 3814 | 15 | 57 | 64 | 28429 | 1000 | 15821 | 13005 | 13893 | 1000 | 1000 | 1000 | 28859 | 28896 | 29030 | 28888 | 28876 |
62004 | 28864 | 232 | 24 | 0 | 0 | 20 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4842 | 28573 | 1 | 0 | 17746 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10904 | 8000 | 0 | 3 | 1 | 8 | 21702 | 28488 | 28717 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 28670 | 28705 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 13297 | 9559 | 6896 | 3160 | 9 | 56 | 20180 | 3249 | 3811 | 16 | 58 | 48 | 28361 | 1000 | 15704 | 12946 | 13603 | 1000 | 1000 | 1000 | 28692 | 28806 | 28966 | 28811 | 28765 |
62004 | 28723 | 230 | 23 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4803 | 28637 | 1 | 1 | 17673 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10900 | 8000 | 0 | 7 | 1 | 8 | 21734 | 28539 | 28654 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 28672 | 28829 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 0 | 0 | 0 | 1000 | 3 | 0 | 222 | 13001 | 9209 | 6890 | 3134 | 11 | 60 | 20515 | 3331 | 3809 | 29 | 55 | 57 | 28528 | 1000 | 15736 | 12957 | 14183 | 1000 | 1000 | 1000 | 29046 | 29001 | 29094 | 29095 | 28949 |
62004 | 29068 | 233 | 19 | 0 | 0 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4542 | 28914 | 0 | 0 | 18030 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10907 | 8000 | 0 | 5 | 0 | 0 | 21727 | 28824 | 29084 | 3 | 30 | 3000 | 1000 | 1001 | 3000 | 1000 | 29096 | 29103 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 4 | 3 | 0 | 1000 | 0 | 0 | 385 | 1000 | 3 | 0 | 0 | 13141 | 9207 | 6848 | 3114 | 7 | 55 | 20555 | 3267 | 3809 | 13 | 57 | 57 | 28608 | 1000 | 16064 | 13034 | 14101 | 1000 | 1000 | 1000 | 29118 | 29142 | 29310 | 29132 | 29046 |
62004 | 29142 | 235 | 19 | 1 | 0 | 24 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4664 | 28960 | 1 | 0 | 17985 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10904 | 8000 | 0 | 8 | 0 | 0 | 21754 | 28590 | 29039 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 28882 | 28875 | 1 | 1 | 61001 | 1000 | 1000 | 1003 | 0 | 3 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13214 | 9392 | 6883 | 3151 | 11 | 61 | 20313 | 3254 | 3817 | 10 | 51 | 61 | 28274 | 1000 | 15804 | 12871 | 13907 | 1000 | 1000 | 1000 | 28918 | 28915 | 28869 | 28936 | 28896 |
62004 | 29038 | 232 | 24 | 0 | 0 | 18 | 0 | 1 | 0 | 132 | 1 | 0 | 0 | 4755 | 28846 | 1 | 1 | 18089 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10908 | 8000 | 0 | 8 | 1 | 0 | 21718 | 28704 | 29015 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 1000 | 28840 | 28877 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 1 | 0 | 0 | 1000 | 2 | 0 | 0 | 13134 | 9199 | 6868 | 3143 | 14 | 52 | 20033 | 3218 | 3811 | 19 | 59 | 63 | 28476 | 1000 | 15561 | 12791 | 13777 | 1000 | 1000 | 1000 | 28915 | 29035 | 28910 | 28922 | 28879 |
Count: 8
Code:
st1 { v0.h }[1], [x6], x8 st1 { v0.h }[1], [x6], x8 st1 { v0.h }[1], [x6], x8 st1 { v0.h }[1], [x6], x8 st1 { v0.h }[1], [x6], x8 st1 { v0.h }[1], [x6], x8 st1 { v0.h }[1], [x6], x8 st1 { v0.h }[1], [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 1 | 80025 | 0 | 8 | 0 | 25 | 240104 | 80100 | 80004 | 80000 | 80104 | 80004 | 80000 | 4359034 | 3758848 | 640028 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 18 | 0 | 0 | 80000 | 1 | 0 | 5 | 80001 | 1 | 17 | 0 | 5110 | 1 | 16 | 0 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 12 | 3 | 1 | 0 | 0 | 80025 | 8 | 8 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 4 | 80001 | 1 | 17 | 0 | 5112 | 2 | 16 | 0 | 2 | 2 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 80025 | 0 | 8 | 0 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 0 | 0 | 0 | 80001 | 1 | 7 | 2 | 80001 | 1 | 17 | 0 | 5112 | 2 | 16 | 0 | 2 | 2 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 30 | 0 | 0 | 0 | 0 | 80025 | 8 | 0 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 0 | 0 | 0 | 80001 | 0 | 0 | 2 | 80000 | 1 | 0 | 0 | 5112 | 2 | 16 | 0 | 2 | 2 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 80025 | 0 | 8 | 0 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 0 | 0 | 0 | 80001 | 2 | 0 | 2 | 80000 | 0 | 17 | 0 | 5112 | 1 | 16 | 0 | 1 | 2 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 1 | 80025 | 8 | 8 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 0 | 80001 | 1 | 0 | 0 | 5110 | 1 | 16 | 0 | 2 | 2 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 80025 | 8 | 0 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 0 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 5112 | 1 | 16 | 0 | 2 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80162 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 21 | 3 | 0 | 0 | 0 | 80147 | 8 | 8 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80000 | 0 | 0 | 2 | 80001 | 1 | 0 | 0 | 5112 | 2 | 16 | 0 | 1 | 1 | 80037 | 80093 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 80025 | 8 | 8 | 1 | 25 | 240100 | 80100 | 80000 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 0 | 0 | 0 | 80001 | 0 | 0 | 1067 | 80001 | 1 | 17 | 0 | 5112 | 1 | 16 | 0 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 12 | 3 | 0 | 0 | 0 | 80025 | 8 | 0 | 3 | 25 | 240100 | 80100 | 80116 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640000 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 80000 | 80040 | 80285 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 18 | 0 | 0 | 80001 | 1 | 0 | 0 | 80001 | 1 | 17 | 0 | 5112 | 2 | 16 | 0 | 2 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 3 | 0 | 0 | 0 | 80025 | 11 | 11 | 3 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4408639 | 3862540 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 0 | 0 | 0 | 5020 | 18 | 16 | 18 | 9 | 80037 | 80000 | 36 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 80025 | 11 | 11 | 2 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 5 | 80001 | 0 | 17 | 0 | 0 | 5020 | 34 | 16 | 17 | 18 | 80037 | 80000 | 19 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 2 | 0 | 0 | 0 | 80025 | 11 | 10 | 1 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 1 | 0 | 2 | 80001 | 1 | 20 | 0 | 0 | 5020 | 19 | 16 | 19 | 14 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 80025 | 8 | 8 | 3 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 25 | 0 | 0 | 80008 | 0 | 0 | 11 | 80001 | 8 | 25 | 7 | 1 | 5020 | 19 | 16 | 18 | 18 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 1 | 80025 | 8 | 8 | 3 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 0 | 0 | 0 | 80000 | 0 | 0 | 3 | 80001 | 0 | 17 | 0 | 0 | 5020 | 18 | 16 | 18 | 19 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 12 | 7 | 0 | 0 | 1 | 80025 | 11 | 9 | 1 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358413 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 4 | 80001 | 1 | 18 | 0 | 0 | 5020 | 16 | 43 | 10 | 20 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 80025 | 11 | 0 | 1 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4360753 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 8 | 25 | 0 | 0 | 80008 | 1 | 0 | 8 | 80001 | 8 | 25 | 7 | 0 | 5020 | 18 | 16 | 18 | 10 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80162 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 80025 | 8 | 0 | 45 | 25 | 240010 | 80010 | 80000 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 640000 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 80000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80061 | 0 | 0 | 2 | 80001 | 0 | 0 | 0 | 0 | 5020 | 17 | 16 | 8 | 17 | 80037 | 80000 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
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