Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (single, post-index, S)

Test 1: uops

Code:

  st1 { v0.s }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f23243a3f464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
620062955023741201210001004650293480118727300010001000100010001000100050001090380008217142926529605310300010001000300010002882128844116100110001000100213010010011000101001304893986854319106020398315338171562572835410001567412760140061000100010002896828898290112890328992
620042895823101120210001004636287670018014300010001000100010001000100050001090780000216752870528955310300010001000300010002900329006116100110001000100230110010111000131101325192186884311305020243319938161860592844510001595913098139431000100010002883728830288912890629009
620042890523301110210001004710287730017923300010001000100010001000100050001090180005217082878628958310300010001000300010002897228932116100110001000100123010010111000131101307193116920310305820162319638151753552840810001572212882140641000100010002892728947289662900228947
620042892223301010000113220046682882400180623000100010001000100010001000500010904800010217232869028978310300010001000300010002886328983116100110001000100320110010011000101001317892796894312925720319325538141958602853110001589312821140321000100010002906528914289962892129091
62004289792320101010001322004584288330018218300010001000100010001000100050001089880005217762894429269310300010001000300010002895028995116100110001000100213110010111000131101300293306930316505720111320038172357622828810001588512725142251000100010002892528872289062890928749
620042881723201200110001004683286510017769300010001000100010001000100050001090180001217392850028814310300010001000300010002885928843116100110001000100220210010011000101001298895516959316735120161328738141758562852110001613512783141691000100010002882128835287702914028991
620042894623301000210001004646286970017714300010001000100010001000100050001090380008217362846828811310300010001000300010002869228749116100110001000100323010010111000131201306692206977312906320268319238161153542830910001553812815137361000100010002871628839287892873628829
620042891223201000110002004822287510017874300310001001100010001000100050001090380006217252861729338310300010001000300010002937529451116100110001000100223110011111000131001313891456885307616320145320738161960572843110001566012688140011000100010002901028912287882894428865
62004291392440100001001322004684290050018598300010011000100010001000100050001089780007217322888529086310300010001000300010002914129131116100110001000100213110010111000131101308691506962305216520406332238192062602839810001640113279142691000100010002898228963290622897528952
6200429011233010100000611045892888201182073003100010001000100010001000500010906800010217052908128968310300010011001300010002925329253116100110001000100240110010111000131001327293976974310316020456322138161564652848210001569313125140171000100010002897029062289652889128852

Test 2: throughput

Count: 8

Code:

  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f22243a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602068004062110010100020018002588225240100801008000080000801008000080000435899437588486400008001580040800405992435999824010020080000800002002400008000080040800401180201100991001008000080000100800077290180008007800001000511011601180037800008000080000801008004180041800418004180041
16020480040620101100000900080025883252401008010080000800008010080000800004359010375884864000080015800408004059924359998240100200800008000020024000080000800408004011802011009910010080000800001008000972901800080011800017071511011601180037800008000080000801008004180041800418004180041
160204800406210000000012000180025980252401008010080000800008010080000800004359002375884864000080015800408004059924359998240100200800008000020024000080000800408004011802011009910010080000800001008000002100800010008000112100511011601180037800008000080000801008004180041800418004180041
1602048004062010000100070008002588742524036980194801208006080216800008021643590143758848641840802248004080161599243601682404402008012080000200240360800008016480161118020110099100100800008000010080130130273801270310988006082970514512501480140801818000080000801008016480287801648028680285
16020482001638112020212649700080270881465524063480287801168018080216801168054043653103767454641856802228028280160600482660170240440200802398012020024072080239801638004011802011009910010080000800001008000702100800000048000112100511011621180037800008000080000801008004180041800418004180041
16020480040620000000000200080025880252401008010080000800008010080000800004359014375884864000080015800408004059924359998240100200800008000020024000080000800408004011802011009910010080000800001008000002100800010038000112100511011601180037800008000080000801008004180041800418004180041
16020480040620000000000000080025880252401008010080000800008010080000800004359014375884864000080015800408004059924359998240100200800008000020024000080000800408004011802011009910010080000800001008000002100800010048000112100511011601180142800008000080000801008004180041800418004180041
160204800406210000000002000800258812524010080100800008000080100800008000043590103758848640000800158004080040599243599982401002008000080128200240000800008004080040118020110099100100800008000010080007729018000811118000182971511011601180037800008000080000801008004180041800418004180041
1602048004062000000000040008002588325240100801008000080000801008000080000435901437588486400008001580040800405992435999824010020080000800002002400008000080040800401180201100991001008000080000100800000000800011018000112100511011601180037800008000080000801008004180041800418004180041
16020480040620000000000400080025883252401008010080000800008010080116800004359014375884864000080015800408004059924359998240100200800008000020024000080000800408004011802011009910010080000800001008000002100800007038000012100511011611180037800008000080000801008004180041800418004180041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f23243a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)7bmap int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafbcl1d cache miss st nonspec (c0)c2cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600268004062000000000200080025880252400108001080000800008001080000800004358429375884864000005800158004080040599463600202400100208000080000202400008000080040800401180021109101080000800001080000021008000100800011210502009167880037800008000080000800108004180041800418004180041
160024800406210000000040008002588025240010801008000080000800108000080000435842937588486400000080015800408004059946360020240010020800008000020240000800008004080040218002110910108000080000108000002100800010380001100502007169780037800008000080000800108004180041800418004180041
16002480040620000000092000800258802524001080010800008000080010800008000043584293758848640000008001580040800405994636002024001002080000800002024000080000800408004011800211091010800008000010800000210080001012800011210502008166980037800008000080000800108004180041800418004180041
16002480040621000000012200080025883252400108001080000800008001080000800004358429375884864000000800158004080040599463600202400100208000080000202400008000080040800401180021109101080000800001080000021008000101800011210502008168880037800008000080000800108004180041800418004180041
1600248004062100000000400080025081252400108001080000800008001080000800004358429375884864000000800158004080040599463600202400100208000080000202400008000080040800401180021109101080000800001080000021008000106800011210502008168780037800008000080000800108004180041800418004180041
160024800406210000000020008002588147252400108001080232802408001080000800004358429375884864000000800158004080040599463600202400100208000080000202400008000080040800401180021109101080000800001080000021008000103800011210502008169580037800008000080000800108004180041800418004180041
1600248004062100000000200080025883252400108001080000800008001080000800004358429375884864000000800158004080040599463600202400100208000080000202400008000080040800401180021109101080000800001080000021008000101800011210502009168880037800008000080000800108004180041800418004180041
160024800406210000000124000800258812524001080010800008000080010800008000043584293758848640000008001580040800405994636002024001092208000080000202400008000080040800401180021109101080000800001080000021008000100800010210502008168880037800008000080000800108004180041800418004180041
160024800406200000000040008002588125240010800108000080000800108000080000435842937588486400000080015800408004059946360020240010020800008000020240000800008004080040118002110910108000080000108000002100800010380000100502009348880037800008000080000800108004180041800418004180041
1600248004062100000001820008002588025240010800108000080000800108000080000435842937588486400000080015800408004059946360020240010020800008000020240000800008004080040118002110910108000080000108000002100800010180000100502009165880037800008000080000800108004180041800418004180041