Firestorm: ST2 (multiple, 16B) measurements

Code:

  st2 { v0.16b, v1.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64007	29410	236	1	1	1	0	1	2	0	0	0	0	2	1	0	4695	29175	0	0	18381	4000	2000	2000	2000	2000	21608	16000	3	21809	0	29125	29361	3	10	4000	2000	2000	4000	4000	29395	29483	1	1	61001	1000	1000	2002	4	6	1	2002	0	0	2	2000	2	4	2	2	0	13153	9302	7005	3189	0	52	20427	3134	3820	14	49	53	28671	15966	13273	14841	2000	2000	29445	29541	29425	29440	29261
64004	29385	236	0	1	3	1	1	0	0	0	0	0	3	1	0	4767	29222	0	0	18208	4000	2000	2000	2000	2000	21622	16000	5	21819	0	29068	29426	3	10	4000	2000	2000	4000	4000	29398	29406	1	1	61001	1000	1000	2002	2	4	1	2002	0	1	2	2000	2	4	2	2	0	13130	9247	6888	3201	2	53	20439	3296	3816	11	55	52	28753	16048	13049	14878	2000	2000	29416	29361	29420	29352	29319
64004	29476	236	0	1	1	1	1	1	1	0	0	0	2	0	0	4620	29220	2	0	18294	4000	2000	2000	2000	2000	21616	16000	2	21876	0	29129	29374	3	10	4000	2000	2000	4000	4000	29277	29418	1	1	61001	1000	1000	2003	3	4	1	2002	0	1	2	2000	2	4	2	0	0	13125	9362	6956	3119	1	59	20408	3344	3822	17	52	52	28709	16461	13305	15043	2000	2000	29523	29401	29488	29308	29422
64004	29419	236	0	1	0	1	0	1	0	0	0	3	3	0	0	4667	29246	2	0	18218	4000	2000	2000	2000	2000	21615	16000	1	21845	0	29101	29459	3	10	4000	2000	2000	4000	4000	29254	29296	1	1	61001	1000	1000	2002	2	0	1	2002	1	0	2	2000	2	4	2	1	0	13284	9377	6901	3188	1	59	20374	3198	3821	16	53	53	28773	16271	13200	14894	2000	2000	29504	29436	29309	29476	29353
64004	29415	236	0	1	1	1	1	2	1	0	0	0	3	0	0	4633	29214	0	0	18343	4000	2000	2000	2000	2000	21618	16000	4	21856	0	28961	29298	3	10	4000	2000	2000	4000	4000	29344	29308	1	1	61001	1000	1000	2003	3	4	1	2002	0	1	2	2000	2	6	2	0	0	13036	9507	6940	3180	0	58	20517	3364	3817	11	50	50	28530	16164	13124	14974	2000	2000	29409	29316	29532	29496	29458
64004	29406	236	0	1	1	1	1	1	1	0	0	0	3	0	0	4657	29202	2	0	18300	4000	2000	2000	2000	2000	21617	16000	1	21887	0	29058	29366	3	10	4000	2000	2000	4000	4000	29309	29403	1	1	61001	1000	1000	2004	2	6	1	2002	0	1	2	2000	2	4	2	0	0	13216	9244	7005	3178	0	47	20489	3331	3822	11	50	51	28714	16153	13192	14880	2000	2000	29441	29509	29332	29295	29345
64004	29330	235	0	1	1	1	1	1	0	0	0	0	3	0	0	4621	29194	2	0	18366	4000	2000	2000	2000	2000	21608	16000	3	21863	0	29080	29461	3	10	4000	2000	2000	4000	4000	29350	29292	1	1	61001	1000	1000	2003	2	6	0	2002	0	1	2	2000	2	6	2	1	0	13187	9257	6994	3147	0	50	20512	3143	3819	15	55	55	28703	16153	13356	14797	2000	2000	29371	29439	29421	29531	29464
64004	29403	237	0	1	1	1	1	3	1	0	0	0	3	0	0	4592	29232	0	0	18304	4000	2000	2000	2000	2000	21623	16000	4	21769	0	29083	29387	3	10	4000	2000	2000	4000	4000	29374	29393	1	1	61001	1000	1000	2002	2	0	1	2002	0	1	2	2000	2	4	2	1	0	13227	9311	6972	3150	1	57	20397	3320	3816	13	53	47	28729	16001	13272	15258	2000	2000	29330	29577	29478	29407	29341
64004	29424	237	0	1	1	1	1	2	1	0	0	0	2	0	0	4601	29134	2	0	18354	4000	2000	2000	2000	2000	21617	16000	4	21864	0	29064	29542	3	10	4000	2000	2000	4000	4000	29423	29283	1	1	61001	1000	1000	2002	2	6	0	2002	1	1	5	2000	2	4	2	1	0	13175	9326	6977	3225	0	48	20363	3175	3818	8	49	53	28737	16108	13345	14955	2000	2000	29308	29480	29438	29281	29511
64004	29466	237	0	1	2	1	1	2	1	0	0	0	3	0	0	4586	29331	0	0	18343	4000	2000	2000	2000	2000	21613	16000	3	21805	0	29054	29449	3	10	4000	2000	2000	4000	4000	29228	29426	1	1	61001	1000	1000	2003	2	4	1	2002	0	1	2	2000	2	4	2	2	0	13190	9248	6947	3239	0	56	20359	3400	3821	8	57	53	28759	15961	13038	15008	2000	2000	29242	29469	29467	29544	29403

Count: 8

Code:

  st2 { v0.16b, v1.16b }, [x6]
  st2 { v0.16b, v1.16b }, [x6]
  st2 { v0.16b, v1.16b }, [x6]
  st2 { v0.16b, v1.16b }, [x6]
  st2 { v0.16b, v1.16b }, [x6]
  st2 { v0.16b, v1.16b }, [x6]
  st2 { v0.16b, v1.16b }, [x6]
  st2 { v0.16b, v1.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	24	37	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320207	80058	620	0	0	0	0	0	0	0	0	0	3	0	5654	80030	16	16	90	25	324159	100	166480	160004	100	160016	160016	500	2297262	1308605	80024	80045	80044	0	6	17	320132	200	160016	160016	200	320272	320032	80044	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	1	0	2	160002	2	42	0	1	1	1	5116	11	16	0	10	12	80042	160000	160000	100	80046	80045	80045	80046	80046
320204	80044	620	0	0	0	0	0	0	0	0	0	3	0	4556	80030	16	16	0	25	325428	100	164348	160005	100	160016	160016	500	2140711	1304534	80024	80045	80044	0	11	15	320132	200	160016	160016	200	320032	320032	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	44	63	0	160003	0	0	2	160002	2	0	0	1	1	1	5116	12	16	0	9	8	80041	160000	160000	100	80045	80046	80045	80046	80046
320204	80045	621	0	0	0	0	0	0	0	0	132	3	0	4199	80030	16	16	0	25	324438	100	165589	160000	100	160000	160000	500	2158831	1299091	80024	80044	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80044	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	5	160002	2	42	0	0	0	0	5109	13	17	0	11	10	80050	160000	160000	100	80046	80045	80046	80045	80045
320204	80044	620	0	0	0	0	0	0	1	0	0	4	0	4084	80196	16	16	0	25	323991	100	164443	160000	100	160000	160000	500	2078785	1307272	80024	80044	80045	0	3	26	320100	200	160000	160000	200	320000	320000	80044	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	1	0	2	160002	0	0	0	0	0	0	5109	12	17	0	10	9	80050	160000	160000	100	80047	80045	80045	80046	81692
320204	82350	620	0	0	0	0	0	0	0	0	0	3	0	4008	80029	16	16	0	25	327365	100	166292	160000	100	160000	160000	500	2131377	1296266	80023	80045	80044	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	0	0	0	5109	12	17	0	16	12	80041	160000	160000	100	80046	80046	80045	80210	80046
320204	80046	620	0	0	0	0	0	0	0	0	0	3	0	6045	80029	16	16	0	25	326953	100	167023	160000	100	160000	160000	500	2079089	1306387	80024	80046	80044	0	3	27	320100	200	160000	160000	200	320000	320000	80044	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	62	0	160000	0	0	5	160065	2	42	0	0	0	0	5109	12	17	0	13	10	80041	160000	160000	100	80046	80045	80045	80046	80047
320204	80044	621	0	0	0	0	0	0	1	0	561	3	0	5017	80028	16	16	0	25	323278	100	167073	160000	100	160000	160000	500	2090964	1297363	80023	80045	80046	0	9	26	320100	200	160000	160000	200	320000	320000	80044	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	1	0	2	160002	0	0	0	0	0	0	5109	13	17	0	14	11	80041	160000	160000	100	80046	80046	80213	80046	80047
320204	80044	621	0	0	0	0	0	0	0	0	0	3	0	4107	80030	0	16	0	25	326570	100	165862	160000	100	160000	160000	500	2079572	1304080	80023	80045	80044	0	3	27	320100	200	160000	160000	200	320000	320000	80044	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	0	160002	2	0	0	0	0	0	5109	15	17	0	14	14	80042	160000	160000	100	80045	80045	80046	80046	80045
320204	80047	643	0	0	0	0	0	0	0	0	0	3	0	4556	80365	16	16	0	25	326351	100	165477	160000	100	160000	160000	500	2236790	1299656	80024	80045	80045	0	3	26	320100	200	160000	160000	200	320000	320000	80046	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	1	0	2	160002	2	42	0	0	0	0	5109	12	17	0	9	13	80042	160000	160000	100	80045	80045	80046	80046	80046
320204	80045	620	0	0	0	0	0	0	0	0	12	3	0	5647	80030	16	16	0	25	324143	100	164363	160000	100	160000	160000	500	2078437	1306387	80022	80045	80045	0	3	27	320100	200	160120	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	927	160002	2	42	0	0	0	0	5109	14	17	0	16	13	80042	160000	160000	100	80047	80046	80046	80045	80047

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320027	80051	620	1	1	0	0	0	0	0	12	3	0	0	0	7012	1	80037	16	16	0	25	324453	10	160004	160000	10	160000	160000	50	2559835	1301467	80026	0	80044	80050	0	3	26	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160015	14	0	0	0	160016	0	1	16	160002	16	44	14	1	5019	8	17	9	9	80047	0	160000	160000	10	80063	80053	80052	80053	80051
320024	80050	621	1	1	0	0	1	0	0	12	19	0	0	0	2429	1	80035	16	16	0	25	322444	10	163636	160000	10	160000	160000	50	2399831	1300398	80028	0	80045	80051	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80051	1	1	80021	10	9	10	10	80000	80000	10	160000	14	42	0	0	160016	0	0	2	160002	16	0	14	0	5019	8	17	10	9	80049	0	160000	160000	10	80053	80045	80045	80051	80046
320024	80052	621	1	0	0	0	0	0	0	0	18	0	0	0	4248	1	80035	16	16	0	25	325847	10	163637	160000	10	160000	160000	50	2079529	1291769	80025	0	80044	80051	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80052	1	1	80021	10	9	10	10	80000	80000	10	160014	14	43	41	0	160016	1	0	20	160000	16	44	14	1	5019	8	17	10	8	80048	0	160000	160000	10	80053	80051	80045	80045	80054
320024	80050	620	0	1	0	0	0	0	0	0	18	0	0	0	4198	0	80047	0	16	0	25	325163	10	166337	160000	10	160000	160000	50	2719786	1306533	80028	0	80045	80051	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80051	1	1	80021	10	9	10	10	80000	80000	10	160000	14	42	0	0	160016	1	0	5	160002	16	42	0	0	5019	10	17	9	6	80059	0	160000	160000	10	80051	80045	80046	80052	80051
320024	80051	620	1	1	0	0	0	0	0	0	14	0	0	0	4194	1	80037	0	16	2	25	325340	10	165614	160000	10	160000	160000	50	2719786	1296436	80027	0	80043	80050	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80050	1	1	80021	10	9	10	10	80000	80000	10	160014	14	44	0	1	160016	0	0	2	160002	2	44	0	0	5019	9	17	8	10	80041	0	160000	160000	10	80053	80046	80046	80053	80045
320024	80052	620	1	0	0	0	0	0	0	12	3	0	0	0	5704	0	80031	16	0	0	25	325881	10	166131	160000	10	160000	160000	50	2159008	1304927	80024	3	80044	80051	0	3	26	320010	20	160000	160000	20	320000	320000	80045	80050	1	1	80021	10	9	10	10	80000	80000	10	160015	15	44	0	0	160016	0	2	19	160002	16	44	14	1	5019	10	17	8	8	80048	0	160000	160000	10	80052	80052	80053	80052	80063
320024	80051	621	1	1	0	0	1	0	0	0	19	0	0	0	6470	1	80047	16	16	0	25	324919	10	164142	160000	10	160000	160000	50	3679454	1291769	80026	0	80045	80052	0	3	25	320010	20	160000	160000	20	320000	320000	80045	80051	1	1	80021	10	9	10	10	80000	80000	10	160014	14	54	0	0	160016	0	0	5	160002	16	44	14	0	5019	10	17	9	8	80048	0	160000	160000	10	80051	80051	80052	80053	80052
320024	80053	621	1	0	0	0	0	0	0	0	18	0	0	0	3782	1	80037	16	16	0	25	324440	10	165843	160000	10	160000	160000	50	2399920	1296549	80026	0	80044	80062	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80052	1	1	80021	10	9	10	10	80000	80000	10	160014	14	44	0	0	160016	2	0	17	160002	16	44	14	0	5019	9	17	8	8	80049	0	160000	160000	10	80052	80046	80046	80052	80046
320024	80051	621	1	1	0	0	0	0	0	0	210	0	0	0	5950	1	80047	16	16	0	25	323408	10	164282	160000	10	160000	160000	50	3679454	1297222	80026	0	80045	80052	0	3	26	320010	20	160000	160000	20	320000	320000	80045	80051	1	1	80021	10	9	10	10	80000	80000	10	160000	14	42	0	0	160016	0	0	2	160002	14	42	0	0	5019	7	17	10	10	80048	0	160000	160000	10	80053	80045	80045	80051	80045
320024	80050	621	0	0	0	0	0	0	0	0	17	0	0	0	3463	0	80029	16	16	0	25	325131	10	164377	160000	10	160000	160000	50	2559849	1296387	80026	0	80044	80050	0	3	26	320010	20	160000	160000	20	320000	320000	80051	80050	1	1	80021	10	9	10	10	80000	80000	10	160014	14	44	0	1	160016	0	0	16	160002	16	44	14	0	5019	10	17	6	10	80060	2	160000	160000	10	80052	80053	80051	80053	80053

ST2 (multiple, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations