Firestorm: ST2 (multiple, 2D) measurements

Code:

  st2 { v0.2d, v1.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	66	69	6b	interrupt pending (6c)	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64007	28627	222	1	0	3	0	0	0	0	0	0	30	0	1	0	0	4800	28443	0	0	17442	4000	2000	2000	2000	2000	21615	16000	15	1	8	0	21821	0	0	28357	28478	3	10	4000	2000	2000	4000	4000	28465	28413	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	0	4	0	0	0	13505	9533	7006	3297	1	36	19604	3314	3808	8	33	36	28095	14879	12516	13622	2000	2000	28512	28467	28557	28541	28439
64004	28611	220	0	0	1	0	0	0	0	0	0	0	1	0	0	0	4933	28548	2	2	17475	4000	2000	2000	2000	2000	21619	16000	11	1	0	0	21841	0	0	28269	28528	3	10	4000	2000	2000	4000	4000	28555	28545	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	0	2	0	0	0	13477	9440	7007	3235	0	37	19490	3245	3811	11	32	40	28114	14878	12553	14017	2000	2000	28669	28588	28585	28373	28557
64004	28486	222	0	0	0	0	0	1	0	0	0	0	1	0	0	0	4807	28369	0	0	17398	4000	2000	2000	2000	2000	21630	16000	8	1	0	0	21856	0	0	28260	28671	3	10	4004	2000	2000	4000	4000	28512	28561	1	1	61001	1000	1000	2000	0	2	0	2000	0	0	0	2000	0	0	0	0	0	13073	9776	7042	3269	1	29	19411	3220	3806	11	35	36	28124	15360	12525	14117	2000	2000	28421	28542	28446	28566	28450
64004	28633	221	0	0	1	0	0	1	0	0	0	0	0	0	0	0	4778	28410	2	0	17387	4000	2000	2000	2000	2000	21613	16000	9	0	0	0	21826	0	0	28372	28516	3	10	4000	2000	2000	4000	4000	28443	28495	1	1	61001	1000	1000	2000	0	0	0	2000	0	0	2	2000	0	0	0	0	0	13564	9471	7020	3167	0	30	19395	3167	3809	8	36	33	28087	15202	12368	13628	2000	2000	28643	28483	28408	28464	28563
64004	28418	220	0	0	1	0	0	1	0	0	0	0	1	0	0	0	4890	28372	0	2	17311	4000	2000	2000	2000	2000	21613	16000	9	0	0	0	21813	0	0	28425	28626	3	10	4000	2000	2000	4000	4000	28455	28599	1	1	61001	1000	1000	2000	0	0	0	2000	0	0	0	2000	0	6	0	0	0	13517	9809	7094	3239	0	31	19446	3260	3802	13	35	26	28190	15104	12419	13819	2000	2000	28668	28514	28539	28494	28497
64004	28511	221	0	0	0	0	0	0	0	0	0	12	0	1	0	0	4923	28166	2	0	17474	4000	2000	2000	2000	2000	21625	16000	16	1	0	0	21819	0	0	28351	28487	3	10	4000	2000	2000	4000	4000	28496	28453	1	1	61001	1000	1000	2000	0	2	0	2000	0	0	0	2000	0	2	0	0	0	13563	9764	7021	3174	0	33	19460	3259	3807	13	33	35	28137	15331	12501	14005	2000	2000	28600	28627	28553	28650	28569
64004	28615	222	0	0	1	0	0	0	0	0	0	0	1	0	0	0	4794	28517	0	0	17505	4000	2000	2000	2000	2000	21619	16000	18	0	0	0	21786	0	0	28446	28610	3	10	4000	2000	2000	4000	4000	28592	28523	1	1	61001	1000	1000	2000	0	6	0	2000	2	0	0	2000	2	6	0	0	0	13084	9420	6960	3199	0	33	19542	3264	3804	12	37	31	28105	15293	12460	14074	2000	2000	28549	28539	28722	28519	28624
64004	28533	221	0	0	2	0	0	2	0	0	0	0	1	0	0	0	4802	28445	2	2	17635	4000	2000	2000	2000	2000	21603	16000	14	0	8	0	21746	0	0	28436	28706	3	10	4000	2000	2000	4000	4000	28540	28538	1	1	61001	1000	1000	2000	0	2	0	2000	0	0	0	2000	0	0	0	0	0	13390	9499	6985	3142	1	28	19563	3172	3804	11	33	31	28125	15324	12596	13953	2000	2000	28553	28605	28635	28590	28538
64004	28569	221	0	0	1	0	0	0	0	0	0	6	3	0	0	0	4863	28449	2	2	17442	4000	2000	2000	2000	2000	21619	16000	16	0	0	0	21792	0	0	28403	28708	3	10	4000	2000	2000	4000	4000	28491	28573	1	1	61001	1000	1000	2000	0	0	0	2000	0	0	2	2000	2	2	0	0	0	13361	9649	7053	3186	0	39	19556	3166	3805	12	34	36	28164	15224	12635	13939	2000	2000	28640	28487	28554	28520	28496
64004	28450	222	0	0	1	0	0	3	0	0	0	0	0	1	0	0	4819	28508	0	0	17458	4000	2000	2000	2000	2000	21618	16000	13	0	0	0	21783	0	0	28419	28665	3	10	4000	2000	2000	4000	4000	28546	28701	1	1	61001	1000	1000	2000	0	0	0	2000	0	0	0	2000	0	2	0	0	0	13254	9399	7022	3208	0	38	19562	3140	3804	15	33	33	28223	15319	12683	14259	2000	2000	28620	28528	28593	28595	28671

Count: 8

Code:

  st2 { v0.2d, v1.2d }, [x6]
  st2 { v0.2d, v1.2d }, [x6]
  st2 { v0.2d, v1.2d }, [x6]
  st2 { v0.2d, v1.2d }, [x6]
  st2 { v0.2d, v1.2d }, [x6]
  st2 { v0.2d, v1.2d }, [x6]
  st2 { v0.2d, v1.2d }, [x6]
  st2 { v0.2d, v1.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	20	22	23	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320207	80071	643	0	0	0	0	0	0	0	12	0	0	1	0	0	5477	0	80030	16	0	13	25	325577	100	165529	160000	100	160000	160000	500	2399049	1302015	0	80100	80048	80044	89	3	31	320100	200	160000	160000	200	320000	320000	80123	80052	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	38	0	0	160000	0	0	12	160063	2	34	0	1	1	5109	1	17	1	1	80043	0	0	160000	160000	100	80046	80046	80046	80045	80044
320204	80044	642	0	0	0	0	0	0	0	0	3	0	0	0	0	3433	0	80029	0	16	0	25	324668	100	165919	160000	100	160000	160000	500	2239519	1295975	0	80023	80046	80046	0	3	27	320100	200	160000	160000	200	320000	320000	80044	80044	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	0	0	0	160000	0	0	2	160002	2	0	0	0	0	5109	1	17	1	1	80041	0	0	160000	160000	100	80046	80045	80045	80046	80045
320204	80049	643	0	0	0	0	0	0	0	0	9	0	0	0	0	2918	0	80028	16	16	0	25	325784	100	164018	160000	100	160000	160000	500	2239608	1306533	0	80024	80044	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	34	0	0	160000	0	0	2	160000	2	34	0	0	0	5109	1	17	1	1	80041	0	0	160000	160000	100	80046	80046	80045	80050	80045
320204	80044	643	0	0	0	0	0	0	0	0	3	0	0	0	0	4001	0	80033	16	16	0	25	325672	100	165335	160000	100	160000	160000	500	2079108	1294680	0	80024	80049	80049	0	3	26	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	34	0	0	160002	1	0	2	160002	2	34	0	0	0	5109	1	17	1	1	80041	0	0	160000	160000	100	80046	80046	80045	80045	80046
320204	80049	643	0	0	0	0	0	0	0	0	9	0	0	0	0	4628	0	80030	16	0	0	25	324528	100	166865	160000	100	160000	160000	500	2079102	1302154	0	80023	80045	80045	0	3	31	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	8	160002	0	34	0	0	0	5109	1	17	1	1	80041	0	0	160000	160000	100	80049	80046	80045	80050	80046
320204	80045	643	0	0	0	0	0	0	0	0	6	0	0	0	0	5798	0	80029	0	0	0	25	324470	100	163584	160000	100	160000	160000	500	2239723	1303364	0	80023	80049	80052	0	3	27	320100	200	160000	160136	200	320000	320000	80044	80044	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	36	0	0	160002	0	0	5	160002	2	0	0	0	0	5109	1	17	1	1	80045	0	0	160000	160000	100	80046	80050	80046	80046	80045
320204	80043	642	0	0	0	0	0	0	0	0	3	0	0	0	0	4411	0	80030	16	0	0	25	327104	100	166005	160000	100	160000	160000	500	2343939	1296933	0	80024	80049	80045	0	3	28	320100	200	160000	160000	200	320000	320000	80044	80044	1	1	80201	100	99	1	100	100	80000	80000	100	160000	0	34	0	0	160002	1	0	2	160002	2	0	0	0	0	5109	1	17	1	1	80042	0	0	160000	160000	100	80046	80046	80045	80045	80044
320204	80043	643	0	0	0	0	0	0	0	0	3	0	0	0	0	7265	0	80030	0	16	0	25	325077	100	166720	160000	100	160000	160000	500	2158783	1296454	0	80024	80045	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80048	80045	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	36	0	0	160002	0	0	3	160002	2	34	0	0	0	5109	1	17	1	1	80042	0	0	160000	160000	100	80047	80045	80046	80045	80049
320204	80049	643	0	0	0	0	0	0	0	3	3	0	0	0	1	5862	0	80030	16	16	0	25	324946	100	164955	160000	100	160000	160000	500	2079378	1297231	0	80023	80045	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80044	80048	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	40	0	0	160002	1	0	8	160000	0	34	0	0	0	5109	1	17	1	1	80041	0	0	160000	160000	100	80049	80046	80047	80050	80046
320204	80044	643	0	0	0	0	0	0	0	0	0	0	0	0	1	4556	0	80029	16	0	0	25	327315	100	165710	160000	100	160000	160000	500	2158259	1295946	0	80025	80045	80045	0	3	31	320100	200	160000	160000	200	320000	320000	80045	80122	1	1	80201	100	99	0	100	100	80000	80000	100	160000	0	34	0	0	160000	0	0	2	160002	0	0	0	0	0	5109	1	17	1	1	80041	0	0	160000	160000	100	80050	80045	80046	80051	80045

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9e	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320027	80059	620	1	0	1	0	0	0	0	18	17	1	0	0	4298	1	80047	16	16	0	25	323312	10	165055	160000	10	160000	160000	50	2639707	1296529	0	5	80026	80052	80052	0	3	45	320010	20	160000	160000	20	320000	320000	80052	80053	1	1	80021	10	9	10	10	80000	80000	0	10	160014	14	44	0	0	160016	0	0	19	160000	16	44	14	0	0	5173	1	17	1	1	80059	160000	160000	10	80054	80052	80052	84019	80053
320024	80666	642	1	0	0	1	1	0	0	39	18	1	0	0	1950	1	80035	16	16	1	25	324010	10	164785	160000	10	160000	160000	50	2479902	1299508	0	0	80034	80050	80050	0	3	33	320010	20	160000	160000	20	320000	320000	80058	80050	1	1	80021	10	9	10	10	80000	80000	6	10	160014	14	36	0	5	160016	6	0	18	160002	16	36	14	0	1	5019	1	17	3	2	80055	160000	160000	10	80052	80067	80228	80051	80060
320024	80050	621	1	0	0	0	0	0	0	0	20	0	0	1	6093	1	80035	16	16	0	25	324716	10	167051	160000	10	160000	160000	50	3679304	1296077	0	0	80033	80050	80051	0	3	40	320010	20	160000	160000	20	320000	320000	80059	80161	1	1	80021	10	9	10	10	80000	80000	0	10	160014	14	2	0	0	160016	0	0	21	160002	16	0	14	0	0	5019	1	26	1	1	80047	160000	160000	10	80059	80051	80060	80051	80053
320024	80060	621	1	0	1	0	0	0	0	0	15	0	1	0	5048	1	80035	0	16	0	25	327250	10	164690	160000	10	160000	160000	50	3679139	1299155	0	0	80027	80059	80058	0	3	31	320010	20	160000	160000	20	320000	320000	80051	80217	1	1	80021	10	9	10	10	80000	80000	0	10	160016	15	36	0	0	160016	0	1	18	160002	16	34	14	2	0	5019	1	17	1	1	80056	160000	160000	10	80059	80061	80052	80051	80062
320024	80058	621	1	0	0	0	0	0	0	0	18	0	0	0	1216	1	80035	16	16	0	25	325663	10	163001	160000	10	160000	160000	50	2399889	1311346	0	0	80028	80059	80048	0	3	32	320010	20	160000	160000	20	320000	320000	80050	80051	1	1	80021	10	9	10	10	80000	80000	0	10	160015	15	36	0	1	160016	1	0	20	160002	16	36	14	0	0	5019	1	17	1	1	80047	160000	160000	10	80051	80059	80060	80051	80059
320024	80050	620	1	0	0	0	0	0	0	0	19	0	1	0	2434	1	80033	16	16	0	25	325908	10	164440	160000	10	160118	160000	50	3599365	1297807	0	0	80025	80050	80050	0	3	40	320010	20	160000	160000	20	320000	320000	80058	80049	1	1	80021	10	9	10	10	80000	80000	0	10	160074	14	36	0	0	160016	0	0	18	160002	14	0	14	0	0	5019	1	17	1	1	80047	160000	160000	10	80059	80050	80053	80051	80059
320024	80059	621	1	0	0	0	0	0	0	0	14	0	1	0	6860	1	80036	16	16	0	25	325692	10	161216	160000	10	160000	160000	50	2239934	1300810	0	0	80027	80050	80058	0	3	34	320010	20	160000	160120	20	320000	320000	80059	80058	1	1	80021	10	9	10	10	80000	80000	0	10	160015	15	36	0	1	160016	0	0	20	160002	16	0	14	0	0	5019	1	17	1	1	80055	160000	160000	10	80052	80059	80050	80051	80060
320024	80058	620	1	0	1	0	0	0	0	0	17	0	1	0	2221	1	80043	16	16	0	25	326628	10	164236	160000	10	160000	160000	50	2156955	1295622	0	0	80025	80060	80060	0	3	32	320010	20	160000	160000	20	320000	320000	80058	80050	1	1	80021	10	9	10	10	80000	80000	0	10	160014	14	36	0	0	160016	0	0	17	160002	14	36	14	0	0	5019	1	17	1	1	80048	160000	160000	10	80059	80061	80051	80059	80069
320024	80059	621	1	0	0	0	0	0	0	0	18	0	1	0	5272	1	80035	16	15	0	25	326091	10	164367	160000	10	160000	160000	50	3679356	1294158	0	0	80035	80058	80058	0	3	50	320010	20	160000	160000	20	320000	320000	80060	80059	1	1	80021	10	9	10	10	80000	80000	0	10	160016	14	0	0	0	160014	0	2	14	160002	16	36	14	0	0	5019	1	17	1	1	80047	160000	160000	10	80059	80051	80060	80060	80053
320024	80050	620	1	0	0	0	0	0	0	12	20	0	1	0	6530	1	80035	16	16	0	25	324715	10	163427	160000	10	160000	160000	50	2639838	1290705	0	0	80034	80049	80050	0	3	32	320010	20	160000	160000	20	320000	320000	80058	80050	1	1	80021	10	9	10	10	80000	80000	0	10	160015	14	38	0	0	160016	1	0	19	160002	16	36	14	0	0	5019	1	17	1	1	80056	160000	160000	10	80062	80053	80059	80060	80051

ST2 (multiple, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations