Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST2 (multiple, 2S)

Test 1: uops

Code:

  st2 { v0.2s, v1.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e1f223a3f464951schedule uop (52)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)5e5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)f5f6f7f8fd
620062840621102101500215107281031017173200010001000100010001090480000102175227857280663102000100010002000200028406283241161001100010001002232100111410001010140691046972323405955199003364380722505328025145691221413399100010002828128327283572819128064
6200428220212119019102049492807701172132000100010001000100010908800001021746279652833431020001000100020002000281962818911610011000100010022221001021100010101402510245714834461050194643234381114494727861142411206313111100010002813628190284002829328359
620042825321112212110105048283110117332200010001000100010001090380000221732281632827431020001000100020002000281602816811610011000100010013021002011100012111384910493722635391358195303390381615505127906141961208312718100010002831628260281372816528046
620042836421211501510105291283010017166200010001000100010001090480000821722281922843331020001000100020002000280052802511610011000100010012321001021100013111389210502728634001149198413373380420495128052147901207813208100010002817328052281752854128196
62004282022111192151010513428233011705920001000100010001000109068000042172728078280823102000100010002000200028274283381161001100010001003321100101110011312136001008571273489855199173375381116545128032149781237213262100010002812428183282182830428350
620042843121212212000105085283911117075200010001000100010001090780000621757280612825531020001000100020002000281612825811610011000100010000001000000100002001380110133732034401453195233444381820475427766141461226113593100010002821728468282192815628240
620042835121201802000005071281071017369200010001000100010001090580000021758279502851631020001000100020002000281802827411610011000100010000201000000100002001415110459715533671048196783303381923484927889142871234313123100010002825628274281852818828100
62004283982120190180000502528362111724720001000100010001000109098000022172328086279893102000100010002000200028206282321161001100010001000030100000010000300140241016672173447955197203242381218504927952141771218312961100010002824728015282532829428302
62004282092130160170000496328126001702020001000100010001000109078000092176227966282583102000100010002000200028352284131161001100010001000030100010010000000142731048871993497949197903252381712465628453158191308514576100010002866228799288602893128592
620042873522401702100105016279990017724200010001000100010001091180000721693283202887231020001000100020002000285332869111610011000100010000301000000100003001372810543724534781051196753352381914535027958142751208612967100010002821528311282952842328141

Test 2: throughput

Count: 8

Code:

  st2 { v0.2s, v1.2s }, [x6]
  st2 { v0.2s, v1.2s }, [x6]
  st2 { v0.2s, v1.2s }, [x6]
  st2 { v0.2s, v1.2s }, [x6]
  st2 { v0.2s, v1.2s }, [x6]
  st2 { v0.2s, v1.2s }, [x6]
  st2 { v0.2s, v1.2s }, [x6]
  st2 { v0.2s, v1.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f23373f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602064005432100000303969400281600251635351008419480000100800008000050018397126497931400214004340045199593200011601002008000080000200160000160000400424004311802011009910010080000800001008000004208000200280002242051101161240040080000800001004004440043400434004440043
16020440042322000004022224002816160251613161008112880000100800008000050018397126441800400214004440043199593200011601002008000080000200160000160000400434004311802011009910010080000800001008000004208000200380002242051101161140040080000800001004004340043400434004340044
1602044004232200000303208400281616025163032100811888000010080000800005001839712650114040212400434004520111320000160100200800008012020016000016000040043400431180201100991001008000080000100800000420800020028000220051102161140040080000800001004004440044400434024840043
16020440043322000003033864002816161402516185810082932800001008000080000500183971264733804002140043400431995932000016010020080000800002001602401600004004340043118020110099100100800008000010080000044988000200280002242051101253140306080000800001004004440043400444004340043
160204400433230011186127022294039016168425162452100826538012010080116801085111850524646439040255402534040420169152028816054920080000800002001600001604804040140141318020110099100100800008000010080122201888006202138280122244051441341240431180000800001004047240463403114046940445
16020440043322000090013524002716160251636741008125680000100800008010850018456286501740400214004240047199597201131605492008012080240200160238160480404004040121802011009910010080000800001008000004608000000580002242051101162140044080000800001004004640047402574004340047
1602044004532200000308954002916160251635821008397380000100800008000050018397126438960400214004340043199593200011601002008000080000200160000160000400444004211802011009910010080000800001008000004208000200280000242051102161240040080000800001004004340044400434004440044
1602044004432200000301498400271616025161440100828138000010080000800005001839712646931040021400424004319959320001160100200800008000020016000016000040042400431180201100991001008000080000100800000420800020028000220051101161240040080000800001004004440044400444004440044
16020440043322000003015014002716160251618331008143580000100800008000050018397126497810400214004340043199593200011601002008000080000200160000160000400434004211802011009910010080000800001008000004208000200280002242051102161240040080000800001004004440044400434004440044
1602044004331000000302397400280160251629131008189080000100800008000050018397126502240400214004340042199593200011601002008000080000200160000160000400424004311802011009910010080000800001008000004208000200280002242051102162140040080000800001004004340044400434004440046

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f22373f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600264004231100000306784002716160251637711081645800001080000800005018397126440961040021400424004319982032003116001020800008000020160000160000400424004311800211091010800008000010800000420080000002800022420502000916684004008000080000104004440044400444004440044
160024400423100000640136240027161602516049810813718000010800008000050183971264408610400214004340084199820320022160010208000080000201600001600004004340043118002110910108000080000108000004200800020028000224205020009161294004008000080000104004340043400444004340044
16002440043310000093139140028016025161426108109380000108000080000501839712641906104002140042400421998203200231600102080000800002016000016000040043400421180021109101080000800001080000042008006000280002242050200010169104004008000080000104004440044400444004440270
1600244025431100000308714002816160251613721082841800001080000800005018397126473851040021400424004319982032002316001020800008000020160000160000400424004311800211091010800008000010800000420080002005800022420502000916974004008000080000104004440043400444004340044
1600244004231100000304064002816160251615511084510800001080000800005018397126507441040021400424004319982032002316001020800008000020160000160000400424004211800211091010800008000010800000420080002005800022420502000616864003908000080000104004340044400434004340044
160024400433100000030483400281616025161459108510580000108000080000501839712643618104002140042400421998203200231600102080000800002016000016000040042400421180021109101080000800001080000000080002002800022420502000816664003908000080000104004440043400444004340044
16002440042310000003027840028161658949161331108074180000108000080000501839712652750154002140043400421998203200221600102080000800002016000016000040043400431180021109101080000800001080000042008000200280002242050200091611104004008000080000104004440044400444004440044
1600244004331100000304379400271616025161233108136280000108000080000501848028643631104002140042400431998203200231600102080000800002016000016000040042400431180021109101080000800001080000000080002003800022420502000616884004008000080000104004440043400434025840044
160024400423100000030387640028000251614661084496800001080000800005018397126453111040021400434004219982032002316001020800008000020160000160000400434004311800211091010800008000010800000420080002002800002420502000816784004008000080000104004440043400444004340043
16002440043311000003030264002716160251632171081044800001080000800005018397126507900040021400424004319982032002316001020800008000020160000160000400424004211800211091010800008000010800000420080002002800022420502050816994003908000080000104004440043400444004340044