Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st2 { v0.4h, v1.4h }, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 2.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 1e | 1f | 22 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6b | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
62006 | 29288 | 219 | 1 | 18 | 0 | 1 | 16 | 1 | 0 | 0 | 0 | 4547 | 29127 | 0 | 0 | 18328 | 2000 | 1000 | 1000 | 1000 | 1000 | 10906 | 8000 | 10 | 21687 | 0 | 28936 | 29254 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 29202 | 29206 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 0 | 0 | 0 | 1000 | 1 | 0 | 1 | 0 | 12856 | 9236 | 6859 | 3063 | 5 | 42 | 20690 | 3075 | 3814 | 14 | 47 | 43 | 28440 | 16373 | 13451 | 15148 | 1000 | 1000 | 29255 | 29241 | 29227 | 29314 | 29230 |
62004 | 29252 | 219 | 0 | 18 | 0 | 0 | 19 | 0 | 42 | 1 | 0 | 4525 | 29070 | 0 | 0 | 18260 | 2000 | 1000 | 1000 | 1000 | 1000 | 10907 | 8000 | 4 | 21719 | 0 | 28904 | 29274 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 29210 | 29168 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 3 | 0 | 1 | 1001 | 0 | 0 | 1 | 1000 | 1 | 2 | 1 | 0 | 12808 | 9202 | 6818 | 3033 | 8 | 40 | 20673 | 3053 | 3810 | 13 | 44 | 46 | 28408 | 16453 | 13562 | 15029 | 1000 | 1000 | 29358 | 29288 | 29293 | 29350 | 29276 |
62004 | 29376 | 219 | 0 | 21 | 0 | 0 | 17 | 0 | 9 | 1 | 0 | 4626 | 29080 | 0 | 0 | 18235 | 2000 | 1000 | 1000 | 1000 | 1000 | 10902 | 8000 | 5 | 21703 | 0 | 28976 | 29264 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 29162 | 29182 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 2 | 0 | 0 | 12783 | 9125 | 6833 | 3084 | 6 | 39 | 20637 | 3095 | 3810 | 7 | 47 | 46 | 28493 | 16313 | 13433 | 15058 | 1000 | 1000 | 29392 | 29303 | 29288 | 29269 | 29229 |
62004 | 29273 | 220 | 1 | 14 | 1 | 0 | 16 | 1 | 15 | 0 | 0 | 4598 | 29131 | 0 | 0 | 18288 | 2000 | 1000 | 1000 | 1000 | 1000 | 10901 | 8000 | 3 | 21732 | 0 | 28985 | 29250 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 29415 | 29241 | 1 | 1 | 61001 | 1000 | 1000 | 1001 | 2 | 2 | 2 | 1001 | 0 | 1 | 1 | 1000 | 1 | 0 | 1 | 0 | 12982 | 9057 | 6819 | 3029 | 10 | 51 | 20755 | 3151 | 3814 | 7 | 44 | 45 | 28566 | 16284 | 13538 | 15030 | 1000 | 1000 | 29297 | 29329 | 29290 | 29287 | 29306 |
62004 | 29263 | 219 | 0 | 19 | 0 | 0 | 17 | 0 | 48 | 1 | 0 | 4608 | 29089 | 0 | 0 | 18250 | 2000 | 1000 | 1000 | 1000 | 1000 | 10905 | 8000 | 0 | 21680 | 0 | 28919 | 29270 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 29188 | 29219 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 2 | 0 | 0 | 12894 | 9264 | 6857 | 3041 | 7 | 43 | 20575 | 3080 | 3816 | 6 | 40 | 49 | 28463 | 16423 | 13640 | 15042 | 1000 | 1000 | 29273 | 29320 | 29292 | 29284 | 29214 |
62004 | 29199 | 218 | 1 | 21 | 1 | 1 | 17 | 1 | 0 | 0 | 1 | 4484 | 29065 | 0 | 0 | 18326 | 2000 | 1000 | 1000 | 1000 | 1000 | 10901 | 8000 | 5 | 21726 | 0 | 28973 | 29359 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 29246 | 29209 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 2 | 1 | 1001 | 0 | 1 | 1 | 1001 | 1 | 2 | 1 | 0 | 12790 | 9099 | 6813 | 3019 | 7 | 41 | 20562 | 3114 | 3806 | 10 | 42 | 42 | 28478 | 16252 | 13547 | 14974 | 1000 | 1000 | 29224 | 29222 | 29322 | 29189 | 29303 |
62004 | 29142 | 219 | 0 | 20 | 0 | 0 | 16 | 0 | 15 | 1 | 0 | 4547 | 29040 | 0 | 0 | 18314 | 2000 | 1000 | 1000 | 1000 | 1000 | 10904 | 8000 | 0 | 21741 | 0 | 28928 | 29187 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 29271 | 29175 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 2 | 0 | 0 | 12868 | 9094 | 6844 | 3068 | 5 | 43 | 20666 | 3099 | 3815 | 13 | 39 | 46 | 28501 | 16529 | 13428 | 15204 | 1000 | 1000 | 29277 | 29309 | 29201 | 29220 | 29301 |
62004 | 29240 | 219 | 1 | 16 | 1 | 1 | 12 | 1 | 9 | 0 | 0 | 4558 | 29047 | 0 | 0 | 18305 | 2000 | 1000 | 1000 | 1000 | 1000 | 10908 | 8000 | 0 | 21706 | 0 | 29001 | 29255 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 29185 | 29230 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 2 | 1 | 1001 | 0 | 1 | 1 | 1001 | 1 | 2 | 1 | 0 | 12955 | 9232 | 6826 | 3055 | 7 | 40 | 20638 | 3085 | 3808 | 8 | 42 | 41 | 28493 | 16212 | 13455 | 15167 | 1000 | 1000 | 29288 | 29265 | 29269 | 29355 | 29276 |
62004 | 29341 | 219 | 0 | 18 | 0 | 0 | 19 | 0 | 9 | 1 | 0 | 4639 | 29062 | 1 | 0 | 18260 | 2000 | 1000 | 1000 | 1000 | 1000 | 10900 | 8000 | 5 | 21696 | 0 | 28955 | 29282 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 29187 | 29164 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 1 | 0 | 0 | 1000 | 0 | 2 | 0 | 0 | 12720 | 9066 | 6856 | 3056 | 5 | 44 | 20724 | 3089 | 3815 | 9 | 45 | 43 | 28449 | 16470 | 13316 | 15097 | 1000 | 1000 | 29335 | 29345 | 29265 | 29263 | 29295 |
62004 | 29269 | 219 | 1 | 18 | 1 | 1 | 18 | 1 | 0 | 0 | 0 | 4555 | 29122 | 0 | 0 | 18370 | 2000 | 1000 | 1000 | 1000 | 1000 | 10904 | 8000 | 5 | 21694 | 0 | 28939 | 29452 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 29181 | 29085 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 0 | 1 | 1001 | 0 | 1 | 2 | 1000 | 2 | 2 | 1 | 2 | 12889 | 8993 | 6834 | 3050 | 7 | 40 | 20697 | 3067 | 3815 | 15 | 42 | 48 | 28414 | 16375 | 13448 | 15068 | 1000 | 1000 | 29334 | 29232 | 29326 | 29293 | 29266 |
Count: 8
Code:
st2 { v0.4h, v1.4h }, [x6] st2 { v0.4h, v1.4h }, [x6] st2 { v0.4h, v1.4h }, [x6] st2 { v0.4h, v1.4h }, [x6] st2 { v0.4h, v1.4h }, [x6] st2 { v0.4h, v1.4h }, [x6] st2 { v0.4h, v1.4h }, [x6] st2 { v0.4h, v1.4h }, [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5007
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 61 | 69 | 6d | 6e | map stall dispatch (70) | rob full (74) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | cf | d0 | d2 | d5 | map dispatch bubble (d6) | d9 | dd | fetch restart (de) | e0 | e8 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 40043 | 311 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 3969 | 0 | 40028 | 16 | 16 | 0 | 25 | 162453 | 100 | 80939 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 650356 | 0 | 0 | 40021 | 40043 | 40043 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40042 | 40043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 14 | 44 | 0 | 0 | 80016 | 0 | 1 | 14 | 80002 | 2 | 42 | 0 | 0 | 0 | 5110 | 0 | 0 | 5 | 16 | 0 | 3 | 3 | 40039 | 0 | 0 | 80000 | 80000 | 100 | 40044 | 40044 | 40044 | 40043 | 40044 |
160204 | 40043 | 311 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 919 | 0 | 40027 | 16 | 16 | 0 | 49 | 162867 | 100 | 81908 | 80000 | 100 | 80000 | 80000 | 500 | 1839928 | 649237 | 0 | 0 | 40021 | 40042 | 40042 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40043 | 40043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 14 | 44 | 0 | 0 | 80016 | 0 | 1 | 16 | 80002 | 0 | 0 | 0 | 0 | 0 | 5110 | 0 | 0 | 4 | 16 | 0 | 4 | 4 | 40039 | 0 | 0 | 80000 | 80000 | 100 | 40043 | 40044 | 40044 | 40044 | 40043 |
160204 | 40043 | 310 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1460 | 0 | 40028 | 16 | 16 | 0 | 25 | 162501 | 100 | 81386 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 644903 | 0 | 0 | 40021 | 40043 | 40042 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40043 | 40043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 14 | 44 | 0 | 0 | 80016 | 0 | 1 | 18 | 80002 | 14 | 0 | 0 | 0 | 0 | 5110 | 0 | 0 | 3 | 16 | 0 | 3 | 3 | 40040 | 0 | 0 | 80000 | 80000 | 100 | 40044 | 40044 | 40044 | 40044 | 40044 |
160204 | 40043 | 310 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3972 | 0 | 40028 | 16 | 16 | 0 | 25 | 161580 | 100 | 82682 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 645759 | 0 | 5 | 40021 | 40042 | 40043 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40042 | 40043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80014 | 15 | 44 | 0 | 0 | 80016 | 0 | 1 | 21 | 80002 | 0 | 42 | 0 | 0 | 0 | 5110 | 0 | 0 | 4 | 16 | 0 | 5 | 5 | 40039 | 0 | 0 | 80000 | 80000 | 100 | 40044 | 40044 | 40043 | 40043 | 40043 |
160204 | 40042 | 311 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3542 | 0 | 40028 | 16 | 16 | 0 | 25 | 163400 | 100 | 81868 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 649825 | 0 | 0 | 40021 | 40042 | 40042 | 19959 | 0 | 3 | 20000 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40042 | 40042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80014 | 14 | 44 | 98 | 0 | 80016 | 0 | 1 | 17 | 80002 | 2 | 42 | 0 | 0 | 0 | 5110 | 0 | 0 | 3 | 16 | 0 | 3 | 2 | 40040 | 0 | 0 | 80000 | 80000 | 100 | 40044 | 40044 | 40044 | 40043 | 40044 |
160204 | 40043 | 310 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 2774 | 0 | 40027 | 16 | 16 | 0 | 25 | 162345 | 100 | 81408 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 642953 | 0 | 0 | 40021 | 40044 | 40042 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40042 | 40042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 14 | 44 | 0 | 0 | 80016 | 0 | 1 | 17 | 80002 | 2 | 42 | 0 | 0 | 0 | 5110 | 0 | 0 | 3 | 16 | 0 | 3 | 3 | 40039 | 0 | 0 | 80000 | 80000 | 100 | 40043 | 40044 | 40043 | 40044 | 40054 |
160204 | 40052 | 310 | 1 | 1 | 0 | 0 | 0 | 132 | 14 | 0 | 0 | 0 | 2427 | 0 | 40027 | 16 | 16 | 0 | 25 | 161741 | 100 | 83972 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 650451 | 0 | 0 | 40021 | 40044 | 40042 | 19959 | 0 | 3 | 20000 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40042 | 40042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 17 | 44 | 3 | 0 | 80016 | 1 | 1 | 17 | 80002 | 16 | 0 | 0 | 0 | 0 | 5110 | 0 | 4 | 4 | 16 | 0 | 5 | 4 | 40039 | 0 | 0 | 80000 | 80000 | 100 | 40044 | 40043 | 40044 | 40044 | 40043 |
160204 | 40042 | 310 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1365 | 0 | 40028 | 0 | 16 | 0 | 25 | 163536 | 100 | 81231 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 649056 | 0 | 0 | 40028 | 40052 | 40050 | 19967 | 0 | 3 | 20012 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40042 | 40042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 15 | 0 | 0 | 0 | 80016 | 0 | 0 | 14 | 80062 | 2 | 46 | 0 | 0 | 0 | 5110 | 0 | 4 | 3 | 16 | 0 | 5 | 4 | 40040 | 0 | 0 | 80000 | 80000 | 100 | 40043 | 40044 | 40044 | 40043 | 40043 |
160204 | 40042 | 311 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4207 | 0 | 40027 | 0 | 16 | 0 | 25 | 162216 | 100 | 83386 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 642953 | 0 | 0 | 40021 | 40042 | 40042 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40043 | 40043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 15 | 44 | 0 | 1 | 80016 | 0 | 0 | 18 | 80002 | 0 | 42 | 0 | 0 | 0 | 5110 | 5 | 0 | 3 | 16 | 0 | 2 | 3 | 40040 | 0 | 0 | 80000 | 80000 | 100 | 40043 | 40044 | 40044 | 40044 | 40043 |
160204 | 40042 | 310 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 1723 | 0 | 40027 | 16 | 16 | 0 | 25 | 161535 | 100 | 81342 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 645614 | 0 | 0 | 40021 | 40042 | 40042 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40042 | 40042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 14 | 44 | 2 | 0 | 80016 | 0 | 0 | 17 | 80002 | 2 | 42 | 0 | 0 | 0 | 5110 | 0 | 0 | 3 | 16 | 0 | 3 | 3 | 40040 | 0 | 0 | 80000 | 80000 | 100 | 40043 | 40043 | 40044 | 40044 | 40043 |
Result (median cycles for code divided by count): 0.5005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 61 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | cf | d0 | d2 | d5 | map dispatch bubble (d6) | da | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 40053 | 310 | 1 | 1 | 0 | 0 | 0 | 18 | 0 | 1469 | 1 | 40032 | 16 | 16 | 0 | 25 | 164621 | 10 | 81645 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 644502 | 1 | 0 | 40021 | 40043 | 40043 | 19982 | 3 | 20022 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40042 | 40043 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 42 | 0 | 0 | 80002 | 5 | 0 | 0 | 3 | 80000 | 14 | 0 | 14 | 0 | 0 | 5020 | 0 | 0 | 15 | 16 | 0 | 22 | 20 | 40059 | 80000 | 80000 | 10 | 40053 | 40052 | 40053 | 40053 | 40056 |
160024 | 40053 | 310 | 1 | 1 | 0 | 0 | 12 | 19 | 0 | 1529 | 1 | 40047 | 16 | 15 | 1 | 25 | 163147 | 10 | 84742 | 80000 | 10 | 80000 | 80000 | 50 | 1840096 | 651372 | 0 | 0 | 40029 | 40062 | 40054 | 19990 | 3 | 20034 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40052 | 40054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 15 | 44 | 0 | 0 | 80016 | 48 | 0 | 0 | 3 | 80002 | 0 | 42 | 0 | 0 | 0 | 5020 | 0 | 0 | 20 | 16 | 0 | 21 | 20 | 40040 | 80000 | 80000 | 10 | 40043 | 40043 | 40044 | 40044 | 40043 |
160024 | 40042 | 310 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 911 | 0 | 40028 | 0 | 0 | 0 | 25 | 161378 | 10 | 80923 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 642064 | 0 | 0 | 40021 | 40043 | 40043 | 19982 | 3 | 20022 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40042 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 42 | 0 | 0 | 80002 | 9 | 0 | 0 | 9 | 80002 | 0 | 44 | 0 | 0 | 0 | 5020 | 0 | 0 | 22 | 16 | 0 | 21 | 19 | 40040 | 80000 | 80000 | 10 | 40043 | 40043 | 40043 | 40043 | 40044 |
160024 | 40042 | 310 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 1391 | 0 | 40028 | 16 | 16 | 0 | 25 | 161213 | 10 | 84371 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 653485 | 0 | 0 | 40021 | 40043 | 40043 | 19982 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40042 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 42 | 0 | 0 | 80000 | 9 | 0 | 0 | 8 | 80002 | 2 | 0 | 0 | 0 | 0 | 5020 | 0 | 0 | 21 | 16 | 0 | 21 | 19 | 40039 | 80000 | 80000 | 10 | 40043 | 40044 | 40044 | 40044 | 40044 |
160024 | 40042 | 311 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3664 | 0 | 40027 | 16 | 16 | 0 | 25 | 160883 | 10 | 83018 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 648014 | 0 | 0 | 40021 | 40043 | 40043 | 19982 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40043 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 42 | 0 | 0 | 80002 | 4 | 0 | 0 | 14 | 80002 | 2 | 0 | 0 | 0 | 0 | 5020 | 0 | 0 | 19 | 16 | 0 | 13 | 19 | 40039 | 80000 | 80000 | 10 | 40043 | 40044 | 40044 | 40044 | 40044 |
160024 | 40043 | 310 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 1362 | 0 | 40029 | 16 | 16 | 0 | 25 | 163875 | 10 | 81770 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 646656 | 0 | 0 | 40021 | 40043 | 40043 | 19982 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40043 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 42 | 0 | 0 | 80002 | 7 | 0 | 0 | 8 | 80000 | 2 | 42 | 0 | 0 | 0 | 5020 | 0 | 0 | 20 | 16 | 0 | 20 | 19 | 40039 | 80000 | 80000 | 10 | 40044 | 40043 | 40044 | 40044 | 40043 |
160024 | 40043 | 310 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 1365 | 0 | 40028 | 0 | 0 | 0 | 25 | 161114 | 10 | 80772 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 655228 | 0 | 0 | 40021 | 40042 | 40042 | 19982 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40042 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 42 | 0 | 0 | 80000 | 11 | 0 | 0 | 17 | 80002 | 0 | 42 | 0 | 0 | 0 | 5020 | 0 | 0 | 18 | 16 | 0 | 19 | 15 | 40039 | 80000 | 80000 | 10 | 40044 | 40043 | 40044 | 40043 | 40044 |
160024 | 40043 | 310 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3758 | 0 | 40027 | 16 | 16 | 0 | 25 | 161655 | 10 | 81211 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 656185 | 0 | 0 | 40021 | 40042 | 40043 | 19982 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40042 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 42 | 0 | 0 | 80002 | 8 | 0 | 0 | 2 | 80002 | 2 | 42 | 0 | 0 | 0 | 5020 | 0 | 0 | 20 | 16 | 0 | 20 | 11 | 40040 | 80000 | 80000 | 10 | 40043 | 40044 | 40044 | 40043 | 40044 |
160024 | 40042 | 310 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | 1362 | 0 | 40028 | 0 | 16 | 0 | 25 | 165404 | 10 | 80837 | 80000 | 10 | 80000 | 80000 | 50 | 1840000 | 640118 | 0 | 0 | 40021 | 40042 | 40043 | 19982 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40043 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 42 | 0 | 0 | 80002 | 10 | 0 | 0 | 14 | 80002 | 2 | 42 | 0 | 0 | 0 | 5020 | 0 | 0 | 14 | 16 | 0 | 20 | 11 | 40040 | 80000 | 80000 | 10 | 40043 | 40043 | 40043 | 40043 | 40044 |
160024 | 40043 | 310 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 874 | 0 | 40028 | 16 | 16 | 0 | 25 | 160676 | 10 | 83243 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 653523 | 0 | 0 | 40021 | 40042 | 40042 | 19982 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40042 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 42 | 0 | 0 | 80002 | 33 | 0 | 0 | 5 | 80002 | 0 | 42 | 0 | 0 | 0 | 5020 | 0 | 0 | 19 | 16 | 0 | 19 | 15 | 40040 | 80000 | 80000 | 10 | 40043 | 40043 | 40043 | 40044 | 40043 |