Firestorm: ST2 (multiple, 4S) measurements

Code:

  st2 { v0.4s, v1.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64007	29725	238	19	0	24	0	0	0	0	1	0	0	4680	29046	0	0	18222	4000	2000	2000	2000	2000	21607	16000	6	0	0	21830	29133	29412	3	10	4000	2000	2000	4000	4000	29132	29186	1	1	61001	1000	1000	2000	0	4	0	2000	1	0	0	2000	4	0	13178	9339	6942	3215	9	57	20305	3217	3814	20	58	62	28705	16065	13128	14996	2000	2000	29440	29415	29297	29379	29384
64004	29373	235	25	0	26	0	0	0	0	0	0	0	4573	29124	0	0	18295	4000	2000	2000	2000	2000	21608	16000	4	0	0	21769	29099	29406	3	10	4000	2000	2000	4000	4000	29369	29209	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	4	0	13052	9199	6872	3142	12	54	20481	3246	3816	16	54	57	28584	15970	13289	14947	2000	2000	29436	29341	29455	29541	29502
64004	29429	236	23	0	24	0	0	0	0	1	0	0	4755	29175	0	0	18372	4000	2000	2000	2000	2000	21607	16000	8	0	0	21818	29249	29520	3	10	4000	2000	2000	4000	4000	29398	29366	1	1	61001	1000	1000	2000	0	6	0	2000	0	0	3	2000	4	0	13109	9436	6848	3108	9	58	20439	3299	3822	25	54	60	28807	16255	13260	15173	2000	2000	29258	29295	29388	29315	29322
64004	29337	237	23	0	24	0	0	0	0	0	0	0	4655	29280	0	0	18410	4000	2002	2000	2000	2002	21616	16000	3	0	0	21798	29163	29554	3	10	4004	2000	2000	4000	4000	29317	29448	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	4	0	13259	9442	6948	3092	15	60	20552	3300	3823	25	52	64	28882	16238	13392	15018	2000	2000	30566	29799	29519	29538	29636
64004	29767	243	25	1	27	0	6	6	660	528	0	0	4506	30233	0	0	18534	4000	2000	2000	2002	2002	21609	16000	3	0	0	21877	29281	29634	7	10	4004	2000	2000	4000	4000	29437	29508	1	1	61001	1000	1000	2002	0	4	0	2000	0	0	470	2002	4	2	13068	9378	6963	3134	13	58	20690	3319	3823	14	59	55	29160	16248	13362	14962	2000	2000	29591	29810	29535	29536	29863
64004	29529	237	21	1	28	0	1	0	132	89	0	0	4692	29474	2	0	18297	4000	2000	2000	2000	2000	21590	16016	7	0	0	21864	29158	29383	14	10	4004	2000	2000	4000	4008	29333	29437	1	1	61001	1000	1000	2002	0	0	0	2000	0	0	405	2000	4	0	13336	9394	6958	3102	13	58	20748	3302	3826	14	60	55	28763	16035	13112	14789	2000	2000	29573	29441	29361	29445	29423
64004	29574	237	26	0	19	0	0	0	0	1	0	0	4649	29273	0	0	18359	4000	2000	2000	2000	2000	21603	16016	6	0	0	21861	29168	29473	3	10	4000	2000	2000	4000	4000	29393	29397	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	4	0	13138	9550	6919	3218	8	57	20541	3281	3812	19	60	50	28838	15920	13192	14928	2000	2000	29570	29680	29458	29527	29462
64004	29382	236	21	0	20	0	0	0	0	0	0	0	4677	29231	0	0	18462	4004	2000	2000	2000	2000	21622	16016	4	0	0	21888	29129	29465	3	30	4000	2000	2000	4000	4000	29376	29332	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	6	0	13205	9512	6968	3127	4	62	20560	3284	3817	16	58	57	28776	16419	13172	15301	2000	2000	29476	29471	29510	29455	29371
64004	29396	236	21	0	21	0	0	0	12	1	0	0	4750	29203	2	0	18349	4000	2000	2000	2000	2000	21643	16000	9	0	0	21820	29286	29525	7	10	4000	2000	2000	4000	4000	29402	29370	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	4	0	13277	9426	6883	3167	9	51	20416	3264	3816	19	59	61	28850	16219	13095	14807	2000	2000	29443	29521	29529	29529	29418
64004	29402	237	24	0	26	0	0	1	0	1	0	0	4662	29346	0	0	18399	4000	2000	2000	2000	2002	21601	16000	2	0	0	21832	29138	29538	3	10	4000	2000	2000	4000	4000	29488	29508	1	1	61001	1000	1000	2002	0	4	0	2000	0	2	0	2000	4	0	13154	9222	6938	3166	11	60	20399	3269	3819	22	54	59	28952	16051	13422	15005	2000	2000	29476	29502	29517	29572	29416

Count: 8

Code:

  st2 { v0.4s, v1.4s }, [x6]
  st2 { v0.4s, v1.4s }, [x6]
  st2 { v0.4s, v1.4s }, [x6]
  st2 { v0.4s, v1.4s }, [x6]
  st2 { v0.4s, v1.4s }, [x6]
  st2 { v0.4s, v1.4s }, [x6]
  st2 { v0.4s, v1.4s }, [x6]
  st2 { v0.4s, v1.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320207	80071	620	0	0	0	0	0	18	3	0	6146	0	80030	16	16	0	25	324128	100	164972	160000	100	160000	160000	500	2239703	1295171	80023	80044	80045	0	3	28	320100	200	160000	160000	200	320240	320000	80048	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	5	160002	2	34	0	5109	1	17	1	1	80042	160000	160000	100	80045	80050	80045	80044	80046
320204	80045	620	0	0	0	0	0	12	3	0	6166	0	80030	16	0	0	25	324076	100	163996	160000	100	160000	160000	500	2157518	1294017	80022	80049	80049	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	36	0	0	160002	0	0	11	160002	2	0	0	5109	1	17	1	1	80041	160000	160000	100	80212	80045	80046	80045	80047
320204	80045	621	0	0	0	0	0	0	3	0	5073	0	80030	16	0	0	25	322802	100	163779	160000	100	160000	160108	500	2239720	1298328	80024	80045	80045	82	3	26	320100	200	160000	160000	200	320000	320000	80045	80049	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	2	160002	2	34	0	5109	1	17	1	1	80041	160000	160000	100	80121	80045	80050	80045	80046
320204	80045	620	0	0	0	0	0	3696	9	0	4448	0	80034	16	16	90	25	326280	100	163557	160000	100	160000	160000	500	2078732	1304893	80024	80044	80044	0	3	30	320100	200	160000	160000	202	320000	320000	80049	80049	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	1	0	11	160002	4	34	0	5109	1	17	1	1	80202	160000	160000	100	80050	80045	80045	80217	80046
320204	80049	620	0	0	0	0	0	24	3	0	4166	0	80029	16	0	0	25	326538	100	163630	160000	100	160000	160000	500	2239765	1297129	80023	80049	80049	0	3	28	320100	200	160000	160000	200	320000	320000	80044	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	2	34	0	0	160002	1	0	2	160002	4	34	0	5109	1	17	1	1	80042	160000	160000	100	80045	80046	80050	80045	80045
320204	80210	620	0	0	0	0	0	0	3	0	4646	0	80034	16	16	0	25	325911	100	164997	160000	100	160000	160000	500	2395916	1298738	80023	80048	80049	0	3	30	320326	200	160000	160000	200	320000	320000	80045	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	8	160002	2	34	0	5109	1	17	1	1	80041	160000	160000	100	80045	80047	80046	80045	80049
320204	80044	621	0	0	0	0	0	132	3	0	2589	0	80029	0	16	0	25	323952	100	163334	160000	100	160000	160000	500	2239720	1293719	80024	80049	80052	0	3	27	320100	202	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	1	0	922	160002	2	34	0	5109	1	17	1	1	80042	160000	160000	100	80047	80046	80050	80046	80045
320204	80044	620	0	0	0	0	0	0	3	0	6132	0	80203	16	16	0	25	326245	100	165725	160000	100	160000	160000	500	2079557	1294068	80024	80044	80045	0	3	26	320100	200	160000	160000	200	320000	320000	80210	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	2	0	3	160002	2	34	0	5109	1	17	1	2	80041	160000	160000	100	80213	80045	80046	80045	80045
320204	80044	620	0	0	0	0	0	0	3	0	4338	0	80030	16	16	0	25	326392	100	169707	160000	100	163186	163240	522	2265387	1303669	80023	80044	80045	0	19	326	320100	200	160000	160000	200	320000	320000	80044	80047	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	5	160002	2	42	0	5109	1	17	1	1	80042	160000	160000	100	80046	80046	80045	80045	80045
320204	80088	621	0	0	0	0	0	12	3	0	6571	0	80029	16	16	0	25	323975	100	164597	160000	100	160000	160000	500	2158255	1302357	80023	80044	80121	0	3	27	320100	200	160000	160000	200	320000	320000	80044	80046	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	5109	1	17	1	1	80206	160000	160000	100	80046	80046	80045	80046	80046

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320027	80389	623	0	1	1	1	2	1	264	179	0	0	4500	0	82418	16	16	90	69	325881	10	166324	160060	10	160118	160108	50	2120613	1302675	80331	80377	80210	84	9	220	320236	20	160120	160120	20	320240	320480	80372	80212	3	1	80021	10	9	10	10	80000	80000	10	160120	0	42	62	7	160902	0	2	14670	161022	2	42	0	5048	0	4	26	2	3	80198	160000	160000	10	80545	80046	80218	80381	80210
320024	80540	622	1	1	1	0	1	1	264	88	0	0	6417	0	80030	16	16	0	25	324208	10	165179	160000	10	160000	160000	50	2079408	1294234	80023	80215	80213	0	10	263	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	5019	0	3	17	3	3	80042	160000	160000	10	80046	80274	80046	80045	80046
320024	80044	620	0	0	0	0	0	0	0	4	1	0	3834	0	80030	0	0	0	25	323612	10	166081	160000	10	160000	160000	50	2157237	1293693	80023	80044	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80046	80044	1	1	80021	10	9	10	10	80000	80000	10	160000	14	42	0	0	160002	0	0	2	160002	2	42	0	5019	0	3	17	3	2	80041	160000	160000	10	80046	80063	80045	80046	80046
320024	80044	620	0	0	0	0	0	0	0	0	0	0	5971	0	80030	16	16	0	25	324380	10	165818	160000	10	160000	160000	50	2294975	1300975	80024	80045	80044	0	3	26	320010	20	160000	160000	20	320000	320000	80044	80044	1	1	80021	10	9	10	10	80000	80000	10	160000	14	42	0	0	160002	0	0	5	160000	0	0	0	5019	0	2	17	3	2	80041	160000	160000	10	80046	80046	80045	80046	80045
320024	80044	620	0	0	0	0	0	0	12	3	0	0	3990	0	80030	0	16	0	25	325772	10	166481	160000	10	160000	160000	50	2078321	1295217	80024	80043	80046	0	3	28	320010	20	160000	160000	20	320000	320000	80045	80046	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	0	160000	0	42	0	5019	0	3	17	3	3	80041	160000	160000	10	80047	80046	80045	80047	80046
320024	80045	621	0	0	0	0	0	0	0	3	0	0	4170	0	80030	16	16	0	25	322061	10	164204	160000	10	160000	160000	50	2079241	1294846	80023	80044	80044	0	3	27	320010	20	160000	160000	20	320000	320000	80044	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160000	0	0	0	160000	2	42	0	5019	0	3	17	4	3	80042	160000	160000	10	80045	80052	80045	80046	80046
320024	80045	620	0	0	0	0	0	0	0	3	0	0	4374	0	80031	16	16	0	25	323731	10	165615	160000	10	160000	160000	50	2145910	1299883	80024	80044	80043	0	3	26	320010	20	160000	160000	20	320000	320000	80045	80044	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160000	1	0	2	160002	2	42	0	5019	0	4	17	3	4	80041	160000	160000	10	80046	80046	80046	80046	80045
320024	80045	620	0	0	0	0	0	0	24	3	0	0	4410	0	80029	16	16	0	25	325991	10	163779	160000	10	160000	160000	50	2158737	1292511	80023	80045	80044	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	14	42	0	0	160002	1	0	2	160002	2	42	0	5019	0	3	17	3	3	80042	160000	160000	10	80045	80045	80046	80045	80046
320024	80046	621	0	0	0	0	0	0	0	3	0	0	5911	0	80029	0	16	0	25	324022	10	163834	160000	10	160000	160000	50	2145910	1298738	80024	80046	80044	0	3	27	320010	20	160000	160000	20	320000	320000	80044	80044	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160000	0	0	5	160002	2	42	0	5019	0	2	17	3	2	80041	160000	160000	10	80046	80045	80046	80046	80046
320024	80044	621	0	0	0	0	0	0	0	3	1	0	4278	0	80030	16	16	0	25	322947	10	163839	160000	10	160000	160000	50	2154709	1296793	80023	80043	80045	0	3	26	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	5	160002	2	42	0	5019	0	3	17	2	3	80041	160000	160000	10	80045	80046	80046	80047	80046

ST2 (multiple, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations