Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st2 { v0.8h, v1.8h }, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 60 nops): 4.000
Issues: 4.000
Integer unit issues: 0.000
Load/store unit issues: 2.000
SIMD/FP unit issues: 2.000
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 60 | 61 | 69 | 6b | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
64007 | 29105 | 234 | 1 | 1 | 22 | 0 | 0 | 29 | 1 | 0 | 0 | 3 | 1 | 0 | 0 | 4728 | 28746 | 0 | 2 | 18076 | 4000 | 2000 | 2000 | 2000 | 2000 | 21617 | 16000 | 12 | 0 | 8 | 21804 | 0 | 28820 | 29173 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 4000 | 28783 | 28880 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 0 | 2000 | 0 | 0 | 0 | 2002 | 0 | 4 | 0 | 171 | 13061 | 9370 | 6905 | 3161 | 12 | 56 | 20037 | 3212 | 3810 | 15 | 62 | 58 | 28559 | 15746 | 12900 | 14625 | 2000 | 2000 | 29006 | 29002 | 29142 | 29041 | 28975 |
64004 | 29103 | 233 | 0 | 0 | 20 | 0 | 0 | 23 | 0 | 0 | 0 | 15 | 1 | 1 | 0 | 4635 | 28825 | 0 | 0 | 17985 | 4000 | 2000 | 2000 | 2000 | 2000 | 21620 | 16000 | 7 | 0 | 8 | 21823 | 0 | 28821 | 29106 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 4000 | 29000 | 28969 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 4 | 0 | 0 | 13221 | 9618 | 6837 | 3151 | 11 | 52 | 20164 | 3283 | 3822 | 24 | 55 | 56 | 28473 | 15951 | 13052 | 14557 | 2000 | 2000 | 28990 | 28974 | 29024 | 29129 | 29020 |
64004 | 28991 | 233 | 0 | 0 | 22 | 0 | 0 | 31 | 0 | 0 | 0 | 3 | 1 | 0 | 0 | 4684 | 28930 | 0 | 0 | 17991 | 4000 | 2000 | 2000 | 2000 | 2000 | 21610 | 16000 | 4 | 0 | 0 | 21874 | 0 | 29262 | 29437 | 10 | 29 | 4000 | 2002 | 2002 | 4004 | 4000 | 29453 | 29657 | 2 | 1 | 61001 | 1000 | 1000 | 2000 | 2 | 6 | 2 | 2001 | 0 | 2 | 215 | 2000 | 0 | 6 | 2 | 0 | 13208 | 9437 | 6870 | 3181 | 12 | 54 | 20744 | 3379 | 3805 | 18 | 52 | 50 | 28924 | 16380 | 13467 | 15068 | 2000 | 2000 | 29710 | 29669 | 29547 | 29596 | 29688 |
64004 | 29627 | 238 | 0 | 0 | 21 | 1 | 0 | 28 | 0 | 2 | 3 | 132 | 0 | 0 | 0 | 4589 | 29512 | 2 | 2 | 18585 | 4008 | 2000 | 2002 | 2002 | 2000 | 21633 | 16016 | 6 | 0 | 8 | 21921 | 0 | 29415 | 29767 | 10 | 10 | 4000 | 2000 | 2002 | 4000 | 4008 | 29749 | 29629 | 2 | 1 | 61001 | 1000 | 1000 | 2004 | 0 | 6 | 5 | 2000 | 0 | 0 | 493 | 2002 | 0 | 0 | 0 | 0 | 13251 | 9414 | 6941 | 3177 | 13 | 55 | 20537 | 3286 | 3816 | 16 | 57 | 53 | 28780 | 16109 | 13379 | 14933 | 2000 | 2000 | 29733 | 29454 | 29469 | 29487 | 29686 |
64004 | 29569 | 236 | 0 | 0 | 21 | 0 | 0 | 25 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 4683 | 29255 | 0 | 2 | 18384 | 4000 | 2000 | 2000 | 2000 | 2000 | 21628 | 16000 | 9 | 0 | 0 | 21822 | 0 | 28991 | 29409 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 4004 | 29585 | 29695 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 0 | 2000 | 0 | 0 | 486 | 2000 | 0 | 6 | 0 | 0 | 13180 | 9640 | 6944 | 3138 | 15 | 49 | 20469 | 3214 | 3816 | 14 | 60 | 57 | 28748 | 16378 | 13285 | 14742 | 2000 | 2000 | 29424 | 29518 | 29335 | 29272 | 29381 |
64004 | 29348 | 237 | 0 | 0 | 20 | 0 | 0 | 33 | 0 | 0 | 0 | 0 | 112 | 0 | 0 | 4701 | 29167 | 0 | 2 | 18399 | 4000 | 2000 | 2000 | 2000 | 2000 | 21606 | 16000 | 2 | 0 | 0 | 21791 | 0 | 29111 | 29382 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 4000 | 29385 | 29390 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 3 | 2000 | 0 | 6 | 0 | 0 | 12905 | 8881 | 6760 | 3047 | 10 | 56 | 20944 | 3132 | 3815 | 62 | 57 | 53 | 29414 | 16398 | 13208 | 15021 | 2000 | 2000 | 30262 | 30200 | 30340 | 30211 | 30017 |
64004 | 29953 | 242 | 0 | 0 | 25 | 0 | 0 | 30 | 0 | 0 | 0 | 180 | 0 | 0 | 0 | 4800 | 29734 | 2 | 2 | 18810 | 4000 | 2000 | 2000 | 2000 | 2000 | 21622 | 16000 | 5 | 0 | 0 | 21789 | 0 | 29063 | 29283 | 3 | 30 | 4000 | 2000 | 2000 | 4000 | 4000 | 29426 | 29482 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 6 | 2000 | 0 | 6 | 0 | 1026 | 13113 | 9571 | 6965 | 3120 | 8 | 58 | 20528 | 3371 | 3816 | 15 | 57 | 48 | 28770 | 16309 | 13224 | 14793 | 2000 | 2000 | 29491 | 29362 | 29426 | 29438 | 29387 |
64004 | 29439 | 237 | 0 | 0 | 28 | 0 | 0 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4708 | 29284 | 2 | 2 | 18434 | 4000 | 2000 | 2000 | 2000 | 2000 | 21616 | 16000 | 9 | 0 | 0 | 21853 | 0 | 29201 | 29547 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 4004 | 29944 | 30051 | 15 | 1 | 61001 | 1000 | 1000 | 2012 | 4 | 0 | 0 | 2014 | 1 | 0 | 7940 | 2020 | 0 | 0 | 2 | 0 | 12943 | 9222 | 6783 | 3072 | 16 | 51 | 20793 | 3156 | 3807 | 32 | 45 | 52 | 29102 | 16125 | 13402 | 15138 | 2000 | 2000 | 30101 | 29972 | 30027 | 30116 | 30335 |
64004 | 30053 | 242 | 0 | 0 | 21 | 0 | 0 | 31 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4766 | 28728 | 2 | 2 | 17669 | 4000 | 2000 | 2004 | 2000 | 2000 | 21640 | 16000 | 15 | 0 | 8 | 21784 | 0 | 28557 | 28772 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 4000 | 28748 | 28728 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 0 | 13214 | 9295 | 6823 | 3096 | 12 | 59 | 19852 | 3194 | 3818 | 16 | 58 | 54 | 28320 | 15486 | 12739 | 14343 | 2000 | 2000 | 28806 | 28917 | 28730 | 28789 | 28751 |
64004 | 28885 | 223 | 0 | 0 | 29 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 4654 | 28656 | 2 | 0 | 17745 | 4000 | 2000 | 2000 | 2000 | 2000 | 21620 | 16000 | 5 | 1 | 0 | 21811 | 0 | 28603 | 28795 | 8 | 10 | 4000 | 2000 | 2002 | 4000 | 4000 | 28727 | 28753 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 0 | 13085 | 9520 | 6900 | 3136 | 14 | 61 | 19821 | 3215 | 3808 | 12 | 54 | 54 | 28287 | 15717 | 12812 | 14209 | 2000 | 2000 | 28734 | 28811 | 28778 | 28877 | 28883 |
Count: 8
Code:
st2 { v0.8h, v1.8h }, [x6] st2 { v0.8h, v1.8h }, [x6] st2 { v0.8h, v1.8h }, [x6] st2 { v0.8h, v1.8h }, [x6] st2 { v0.8h, v1.8h }, [x6] st2 { v0.8h, v1.8h }, [x6] st2 { v0.8h, v1.8h }, [x6] st2 { v0.8h, v1.8h }, [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0007
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 23 | 37 | 3a | 3f | 46 | 49 | 4f | 50 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320207 | 80070 | 621 | 1 | 0 | 0 | 0 | 0 | 27 | 19 | 0 | 5866 | 1 | 80034 | 16 | 16 | 0 | 0 | 25 | 323658 | 100 | 164822 | 160000 | 100 | 160000 | 160000 | 500 | 3599298 | 1304226 | 0 | 80035 | 80058 | 80059 | 0 | 3 | 32 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 320000 | 80058 | 80059 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 15 | 36 | 1 | 0 | 160016 | 0 | 0 | 29 | 160002 | 16 | 36 | 14 | 1 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80058 | 0 | 160000 | 160000 | 100 | 80051 | 80059 | 80050 | 80051 | 80060 |
320204 | 80050 | 620 | 1 | 0 | 1 | 0 | 0 | 0 | 18 | 0 | 5597 | 1 | 80036 | 16 | 16 | 0 | 0 | 25 | 322723 | 100 | 165288 | 160000 | 100 | 160000 | 160000 | 500 | 3679200 | 1297489 | 0 | 80024 | 80058 | 80058 | 0 | 3 | 32 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 320000 | 80044 | 80050 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 34 | 0 | 0 | 160016 | 1 | 0 | 21 | 160002 | 16 | 36 | 14 | 0 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80047 | 0 | 160000 | 160000 | 100 | 80045 | 80059 | 80051 | 80051 | 80051 |
320204 | 80058 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 21 | 0 | 4770 | 1 | 80045 | 16 | 16 | 0 | 0 | 25 | 325980 | 100 | 160823 | 160000 | 100 | 160000 | 160000 | 500 | 2719841 | 1298306 | 0 | 80025 | 80049 | 80048 | 0 | 3 | 33 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 320000 | 80058 | 80058 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 14 | 36 | 0 | 0 | 160002 | 0 | 0 | 17 | 160002 | 16 | 36 | 14 | 1 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80055 | 0 | 160000 | 160000 | 100 | 80060 | 80050 | 80060 | 80060 | 80051 |
320204 | 80060 | 621 | 1 | 0 | 1 | 0 | 0 | 0 | 20 | 0 | 6343 | 0 | 80036 | 16 | 16 | 0 | 0 | 25 | 325386 | 100 | 161221 | 160000 | 100 | 160134 | 160000 | 500 | 3679304 | 1295275 | 0 | 80035 | 80058 | 80059 | 0 | 3 | 31 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 320000 | 80051 | 80050 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 34 | 0 | 0 | 160016 | 0 | 1 | 17 | 160002 | 16 | 0 | 14 | 0 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80049 | 0 | 160000 | 160000 | 100 | 80061 | 80045 | 80048 | 80051 | 80051 |
320204 | 80061 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 17 | 0 | 4667 | 0 | 80044 | 16 | 16 | 1 | 0 | 25 | 323624 | 100 | 165019 | 160000 | 100 | 160000 | 160000 | 500 | 3679304 | 1290488 | 0 | 80033 | 80058 | 80050 | 0 | 3 | 40 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 320000 | 80044 | 80050 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 14 | 36 | 0 | 0 | 160002 | 0 | 1 | 8 | 160002 | 0 | 34 | 0 | 0 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80056 | 0 | 160000 | 160000 | 100 | 80053 | 80051 | 80060 | 80061 | 80045 |
320204 | 80052 | 621 | 1 | 0 | 0 | 0 | 0 | 12 | 19 | 0 | 582 | 1 | 80044 | 16 | 15 | 0 | 0 | 25 | 325935 | 100 | 164351 | 160000 | 100 | 160000 | 160000 | 500 | 3599164 | 1293512 | 0 | 80026 | 80059 | 80058 | 0 | 3 | 33 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 320000 | 80059 | 80059 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 14 | 36 | 0 | 0 | 160002 | 1 | 0 | 0 | 160002 | 16 | 36 | 14 | 0 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80062 | 0 | 160000 | 160000 | 100 | 80065 | 80053 | 80059 | 80060 | 80051 |
320204 | 80051 | 620 | 1 | 1 | 1 | 0 | 0 | 0 | 19 | 0 | 3444 | 1 | 80044 | 0 | 16 | 0 | 0 | 25 | 323237 | 100 | 162426 | 160000 | 100 | 160000 | 160000 | 500 | 2479917 | 1291644 | 0 | 80033 | 80058 | 80052 | 0 | 13 | 43 | 320100 | 200 | 160120 | 160360 | 200 | 320000 | 320000 | 80048 | 80061 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 15 | 36 | 0 | 0 | 160016 | 0 | 0 | 16 | 160002 | 16 | 36 | 14 | 1 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80047 | 0 | 160000 | 160000 | 100 | 80062 | 80050 | 80051 | 80059 | 80046 |
320204 | 80060 | 621 | 1 | 0 | 1 | 0 | 0 | 0 | 19 | 0 | 2425 | 1 | 80043 | 16 | 16 | 0 | 0 | 25 | 325427 | 100 | 166125 | 160000 | 100 | 160000 | 160000 | 500 | 3679238 | 1295472 | 0 | 80025 | 80062 | 80057 | 0 | 3 | 34 | 320100 | 200 | 160000 | 160000 | 200 | 320272 | 320000 | 80058 | 80058 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 15 | 34 | 0 | 1 | 160016 | 2 | 0 | 20 | 160002 | 16 | 36 | 14 | 1 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80048 | 0 | 160000 | 160000 | 100 | 80046 | 80046 | 80050 | 80060 | 80060 |
320204 | 80058 | 621 | 1 | 0 | 1 | 0 | 0 | 0 | 19 | 0 | 3503 | 1 | 80035 | 16 | 16 | 0 | 0 | 25 | 323910 | 100 | 166580 | 160000 | 100 | 160000 | 160000 | 500 | 3599365 | 1295430 | 0 | 80025 | 80059 | 80059 | 0 | 3 | 39 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 320000 | 80050 | 80051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160257 | 7 | 36 | 0 | 1 | 160016 | 1 | 0 | 16 | 160002 | 16 | 36 | 14 | 0 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80048 | 0 | 160000 | 160000 | 100 | 80053 | 80059 | 80050 | 80051 | 80060 |
320204 | 80058 | 621 | 1 | 1 | 0 | 0 | 0 | 0 | 19 | 0 | 6730 | 1 | 80035 | 16 | 16 | 0 | 0 | 25 | 325901 | 100 | 165636 | 160000 | 100 | 160000 | 160000 | 500 | 3679373 | 1303525 | 0 | 80034 | 80050 | 80059 | 0 | 3 | 39 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 320000 | 80051 | 80049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 36 | 0 | 0 | 160016 | 0 | 0 | 17 | 160002 | 16 | 36 | 14 | 1 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80047 | 0 | 160000 | 160000 | 100 | 80060 | 80062 | 80053 | 80051 | 80061 |
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 61 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d0 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320027 | 80071 | 620 | 1 | 1 | 0 | 1 | 0 | 0 | 12 | 18 | 0 | 2434 | 1 | 80036 | 15 | 0 | 0 | 25 | 325365 | 10 | 166253 | 160000 | 10 | 160000 | 160000 | 50 | 2719799 | 1299968 | 1 | 0 | 80026 | 0 | 80051 | 80063 | 0 | 3 | 34 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 320000 | 80052 | 80050 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160016 | 15 | 0 | 0 | 0 | 160016 | 1 | 1 | 21 | 160002 | 16 | 44 | 14 | 1 | 5019 | 0 | 3 | 17 | 4 | 3 | 80049 | 0 | 160000 | 160000 | 10 | 80053 | 80052 | 80064 | 80052 | 80053 |
320024 | 80052 | 620 | 1 | 0 | 0 | 0 | 0 | 8 | 0 | 14 | 0 | 4313 | 1 | 80035 | 16 | 16 | 0 | 25 | 320014 | 10 | 162948 | 160000 | 10 | 160000 | 160000 | 50 | 2238119 | 1299179 | 1 | 0 | 80025 | 0 | 80050 | 80050 | 0 | 3 | 34 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 320000 | 80050 | 80050 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160014 | 14 | 44 | 0 | 1 | 160016 | 0 | 1 | 14 | 160002 | 16 | 0 | 14 | 3 | 5019 | 0 | 3 | 17 | 3 | 4 | 80206 | 0 | 160000 | 160000 | 10 | 80051 | 80052 | 80053 | 80223 | 80051 |
320024 | 80051 | 621 | 1 | 1 | 0 | 1 | 0 | 0 | 12 | 20 | 0 | 3859 | 1 | 80037 | 16 | 0 | 0 | 25 | 325032 | 10 | 161217 | 160000 | 10 | 160000 | 160000 | 50 | 2399920 | 1293722 | 0 | 0 | 80026 | 0 | 80050 | 80051 | 0 | 7 | 32 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 320000 | 80051 | 80054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160014 | 15 | 0 | 0 | 0 | 160016 | 0 | 1 | 16 | 160000 | 16 | 44 | 14 | 1 | 5019 | 0 | 4 | 26 | 3 | 4 | 80049 | 0 | 160000 | 160000 | 10 | 80052 | 80052 | 80053 | 80052 | 80064 |
320024 | 80053 | 621 | 1 | 0 | 0 | 1 | 0 | 0 | 111 | 17 | 0 | 1677 | 1 | 80036 | 16 | 16 | 0 | 25 | 325880 | 10 | 163668 | 160000 | 10 | 160000 | 160000 | 50 | 2399803 | 1294402 | 1 | 0 | 80026 | 0 | 80050 | 80050 | 0 | 3 | 33 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 320240 | 80052 | 80050 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160014 | 14 | 44 | 0 | 0 | 160016 | 0 | 0 | 25 | 160002 | 16 | 44 | 14 | 1 | 5019 | 0 | 4 | 17 | 3 | 4 | 80049 | 0 | 160000 | 160000 | 10 | 80052 | 80051 | 80052 | 80051 | 80052 |
320024 | 80062 | 620 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 19 | 0 | 8236 | 1 | 80037 | 16 | 16 | 0 | 25 | 324718 | 10 | 164701 | 160000 | 10 | 160000 | 160000 | 50 | 2399831 | 1307011 | 0 | 0 | 80025 | 0 | 80052 | 80050 | 0 | 3 | 127 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 320000 | 80050 | 80052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160015 | 14 | 44 | 2 | 3 | 160016 | 0 | 0 | 17 | 160000 | 16 | 42 | 14 | 0 | 5019 | 0 | 3 | 17 | 4 | 3 | 80049 | 0 | 160000 | 160000 | 10 | 80053 | 80053 | 80052 | 80052 | 80052 |
320024 | 80052 | 621 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 5781 | 1 | 80037 | 16 | 16 | 0 | 25 | 325659 | 10 | 165190 | 160000 | 10 | 160000 | 160108 | 50 | 2479775 | 1303490 | 0 | 0 | 80025 | 0 | 80062 | 80050 | 0 | 3 | 45 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 320000 | 80051 | 80051 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160014 | 14 | 42 | 0 | 1 | 160014 | 0 | 0 | 21 | 160002 | 16 | 0 | 14 | 0 | 5019 | 0 | 3 | 17 | 4 | 3 | 80049 | 0 | 160000 | 160000 | 10 | 80053 | 80052 | 80051 | 80052 | 80053 |
320024 | 80048 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 0 | 11241 | 1 | 80037 | 16 | 16 | 0 | 49 | 324634 | 10 | 164324 | 160000 | 10 | 160000 | 160000 | 50 | 2799785 | 1298641 | 1 | 0 | 80027 | 0 | 80229 | 80050 | 0 | 3 | 33 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 320000 | 80062 | 80062 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160077 | 16 | 44 | 0 | 0 | 160016 | 0 | 0 | 16 | 160000 | 16 | 44 | 14 | 0 | 5019 | 0 | 3 | 17 | 4 | 3 | 80048 | 0 | 160000 | 160000 | 10 | 80053 | 80052 | 80064 | 80052 | 80053 |
320024 | 80051 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 3 | 17 | 0 | 11 | 1 | 80036 | 16 | 16 | 0 | 25 | 324718 | 10 | 164700 | 160000 | 10 | 160000 | 160000 | 50 | 2479775 | 1294572 | 0 | 0 | 80028 | 0 | 80051 | 80050 | 0 | 3 | 33 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 320000 | 80051 | 80051 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160014 | 14 | 44 | 0 | 0 | 160016 | 0 | 1 | 16 | 160002 | 14 | 44 | 14 | 2 | 5019 | 0 | 3 | 17 | 2 | 3 | 80048 | 0 | 160000 | 160000 | 10 | 80052 | 80049 | 80053 | 80052 | 80063 |
320024 | 80051 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 6 | 21 | 0 | 4708 | 1 | 80048 | 16 | 15 | 0 | 25 | 322941 | 10 | 164444 | 160000 | 10 | 160000 | 160000 | 50 | 2641888 | 1303540 | 0 | 0 | 80026 | 0 | 80051 | 80051 | 0 | 7 | 33 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 320000 | 80051 | 80052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160015 | 14 | 0 | 0 | 1 | 160016 | 0 | 3 | 21 | 160002 | 16 | 0 | 14 | 1 | 5019 | 0 | 4 | 17 | 3 | 4 | 80049 | 0 | 160000 | 160000 | 10 | 80048 | 80054 | 80052 | 80052 | 80052 |
320024 | 80050 | 642 | 1 | 1 | 0 | 0 | 0 | 0 | 12 | 14 | 0 | 5893 | 0 | 80029 | 16 | 16 | 0 | 25 | 324207 | 10 | 169187 | 161620 | 10 | 160590 | 160108 | 50 | 2079511 | 1299117 | 1 | 0 | 80026 | 0 | 80051 | 80050 | 0 | 3 | 32 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 320000 | 80050 | 80051 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160015 | 14 | 44 | 0 | 0 | 160016 | 0 | 1 | 20 | 160002 | 14 | 44 | 14 | 1 | 5019 | 0 | 3 | 17 | 3 | 4 | 80048 | 0 | 160000 | 160000 | 10 | 80053 | 80051 | 80052 | 80053 | 80051 |