Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st2 { v0.16b, v1.16b }, [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 4.000
Issues: 5.000
Integer unit issues: 1.000
Load/store unit issues: 2.000
SIMD/FP unit issues: 2.000
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
64007 | 29319 | 234 | 19 | 1 | 1 | 21 | 0 | 3 | 1 | 264 | 176 | 1 | 0 | 4758 | 28934 | 2 | 2 | 18048 | 5000 | 1000 | 2002 | 2002 | 1000 | 2000 | 2002 | 5005 | 21619 | 16016 | 22 | 21790 | 29053 | 29332 | 14 | 27 | 5000 | 2000 | 2004 | 5000 | 4000 | 29315 | 29233 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 0 | 2002 | 0 | 0 | 2000 | 0 | 0 | 0 | 0 | 0 | 13129 | 9267 | 6859 | 3072 | 9 | 76 | 20043 | 3374 | 3796 | 42 | 71 | 64 | 28400 | 1000 | 15501 | 12941 | 13817 | 2000 | 2000 | 1000 | 28660 | 28626 | 28740 | 28896 | 28959 |
64004 | 28886 | 232 | 20 | 0 | 0 | 24 | 0 | 0 | 0 | 18 | 0 | 1 | 0 | 4758 | 28608 | 0 | 2 | 17736 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21619 | 16000 | 28 | 21689 | 28580 | 29003 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 4000 | 28654 | 28581 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 0 | 2000 | 1 | 2 | 2002 | 0 | 0 | 0 | 2 | 2349 | 13155 | 9300 | 6847 | 3143 | 12 | 73 | 19876 | 3271 | 3796 | 37 | 67 | 68 | 28385 | 1000 | 15627 | 12894 | 14143 | 2000 | 2000 | 1000 | 29091 | 29089 | 29045 | 29025 | 29018 |
64004 | 29147 | 233 | 20 | 1 | 0 | 20 | 1 | 2 | 1 | 288 | 193 | 0 | 0 | 4596 | 28952 | 2 | 2 | 18440 | 5045 | 1008 | 2008 | 2016 | 1009 | 2014 | 2012 | 5035 | 22066 | 16128 | 25 | 22086 | 29330 | 29726 | 84 | 290 | 5041 | 2022 | 2006 | 5035 | 4026 | 29235 | 29440 | 16 | 1 | 61001 | 1000 | 1000 | 2008 | 2 | 0 | 4 | 2010 | 1 | 5568 | 2012 | 0 | 6 | 0 | 2 | 0 | 12793 | 8791 | 6693 | 3018 | 15 | 62 | 19931 | 3184 | 3799 | 38 | 65 | 67 | 28470 | 1000 | 15899 | 12667 | 14017 | 2000 | 2000 | 1000 | 29014 | 29025 | 29064 | 29302 | 28900 |
64004 | 28840 | 224 | 17 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4660 | 28720 | 2 | 2 | 17900 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21617 | 16000 | 19 | 21753 | 28760 | 28962 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 4000 | 29030 | 29078 | 2 | 1 | 61001 | 1000 | 1000 | 2004 | 0 | 0 | 0 | 2000 | 0 | 2 | 2000 | 0 | 6 | 0 | 0 | 0 | 13021 | 9068 | 6836 | 3122 | 15 | 73 | 20297 | 3210 | 3801 | 35 | 72 | 64 | 28411 | 1000 | 16163 | 12867 | 14343 | 2000 | 2000 | 1000 | 29161 | 29193 | 29148 | 29030 | 29025 |
64004 | 29024 | 234 | 23 | 0 | 0 | 21 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4613 | 28913 | 2 | 2 | 17974 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21627 | 16000 | 21 | 21762 | 28811 | 29288 | 6 | 28 | 5000 | 2000 | 2000 | 5000 | 4000 | 28981 | 29108 | 2 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 0 | 2000 | 0 | 0 | 2000 | 2 | 0 | 2 | 2 | 0 | 12982 | 9268 | 6864 | 3118 | 13 | 64 | 19905 | 3150 | 3798 | 39 | 71 | 67 | 28701 | 1006 | 15806 | 12785 | 14021 | 2000 | 2000 | 1000 | 29539 | 29610 | 29679 | 29360 | 29639 |
64004 | 29509 | 229 | 21 | 0 | 0 | 19 | 1 | 0 | 1 | 1596 | 1056 | 0 | 0 | 4661 | 29430 | 2 | 2 | 17874 | 5000 | 1000 | 2000 | 2000 | 1007 | 2011 | 2018 | 5040 | 22155 | 16096 | 15 | 21808 | 29114 | 29424 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 4000 | 28972 | 29531 | 14 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 2008 | 0 | 6 | 0 | 0 | 0 | 13037 | 9291 | 6922 | 3109 | 10 | 75 | 20034 | 3101 | 3803 | 51 | 69 | 68 | 29078 | 1000 | 16463 | 13449 | 14751 | 2000 | 2000 | 1000 | 29995 | 30090 | 30095 | 30177 | 29584 |
64004 | 29601 | 239 | 12 | 0 | 0 | 19 | 0 | 0 | 0 | 147 | 1 | 0 | 1 | 4616 | 29235 | 2 | 0 | 18485 | 5000 | 1000 | 2000 | 2000 | 1000 | 2008 | 2010 | 5060 | 22036 | 16096 | 3 | 21841 | 29767 | 30134 | 3 | 10 | 5000 | 2000 | 2000 | 5030 | 4024 | 30018 | 30034 | 15 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 2000 | 0 | 0 | 0 | 0 | 0 | 13265 | 9327 | 6847 | 3088 | 12 | 56 | 20589 | 3282 | 3818 | 34 | 62 | 59 | 28774 | 1000 | 16376 | 13229 | 14638 | 2000 | 2000 | 1000 | 29677 | 29685 | 29652 | 29457 | 29912 |
64004 | 29589 | 228 | 20 | 0 | 1 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 4744 | 29226 | 0 | 0 | 18382 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21614 | 16000 | 3 | 21794 | 29181 | 29629 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 4000 | 29422 | 29468 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 2 | 0 | 2000 | 0 | 0 | 2000 | 0 | 4 | 0 | 0 | 0 | 13260 | 9335 | 6915 | 3087 | 7 | 67 | 20706 | 3357 | 3819 | 37 | 66 | 65 | 28775 | 1000 | 16509 | 13360 | 14593 | 2000 | 2000 | 1000 | 29576 | 29512 | 29539 | 29587 | 29545 |
64004 | 29652 | 229 | 23 | 1 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4663 | 29272 | 0 | 0 | 18463 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5005 | 21611 | 16000 | 2 | 21827 | 29169 | 29553 | 7 | 10 | 5000 | 2000 | 2000 | 5000 | 4000 | 29430 | 29491 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 2 | 4 | 0 | 2000 | 0 | 0 | 2000 | 0 | 0 | 0 | 0 | 0 | 13178 | 9341 | 6907 | 3124 | 9 | 63 | 20632 | 3340 | 3818 | 34 | 63 | 65 | 28869 | 1000 | 16342 | 13338 | 14723 | 2000 | 2000 | 1000 | 29542 | 29681 | 29513 | 29664 | 29610 |
64004 | 29554 | 230 | 22 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 4640 | 29190 | 0 | 0 | 18597 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21605 | 16000 | 6 | 21818 | 29108 | 29609 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 4000 | 29470 | 29543 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 1 | 150 | 2000 | 0 | 4 | 0 | 0 | 0 | 13188 | 9433 | 6892 | 3126 | 9 | 65 | 20431 | 3281 | 3817 | 29 | 63 | 66 | 28595 | 1000 | 16500 | 13216 | 14569 | 2000 | 2000 | 1000 | 29602 | 29543 | 29520 | 29559 | 29488 |
Count: 8
Code:
st2 { v0.16b, v1.16b }, [x6], x8 st2 { v0.16b, v1.16b }, [x6], x8 st2 { v0.16b, v1.16b }, [x6], x8 st2 { v0.16b, v1.16b }, [x6], x8 st2 { v0.16b, v1.16b }, [x6], x8 st2 { v0.16b, v1.16b }, [x6], x8 st2 { v0.16b, v1.16b }, [x6], x8 st2 { v0.16b, v1.16b }, [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320207 | 80071 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1 | 0 | 0 | 2101 | 2 | 80033 | 16 | 16 | 0 | 25 | 403766 | 80100 | 161003 | 160000 | 80100 | 160000 | 160000 | 480499 | 2398532 | 1287750 | 0 | 80025 | 80061 | 80059 | 0 | 3 | 32 | 400100 | 200 | 160000 | 160120 | 200 | 400000 | 320000 | 80049 | 80049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160012 | 13 | 38 | 0 | 0 | 160014 | 1 | 0 | 15 | 160002 | 12 | 0 | 12 | 0 | 5109 | 1 | 17 | 1 | 1 | 80047 | 80000 | 160000 | 160000 | 80100 | 80060 | 80063 | 80050 | 80052 | 80052 |
320204 | 80061 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 1 | 0 | 0 | 3887 | 2 | 80034 | 0 | 16 | 0 | 25 | 401725 | 80100 | 164666 | 160000 | 80100 | 160000 | 160000 | 480499 | 3679188 | 1304737 | 0 | 80034 | 80052 | 80051 | 0 | 3 | 142 | 406663 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80051 | 80051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 0 | 32 | 0 | 0 | 160002 | 0 | 4 | 8 | 160002 | 2 | 32 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80043 | 80000 | 160000 | 160000 | 80100 | 80071 | 80062 | 80052 | 80051 | 80051 |
320204 | 80061 | 620 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | 4333 | 2 | 80041 | 16 | 16 | 0 | 25 | 404902 | 80100 | 166593 | 160000 | 80100 | 160000 | 160000 | 480499 | 2079501 | 1305868 | 0 | 80029 | 80211 | 80049 | 332 | 3 | 31 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80044 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 0 | 32 | 0 | 0 | 160002 | 0 | 0 | 5 | 160002 | 2 | 32 | 0 | 0 | 5122 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80048 | 80046 | 80051 | 80046 | 80046 |
320204 | 80045 | 621 | 0 | 0 | 0 | 0 | 1 | 0 | 3 | 0 | 0 | 0 | 0 | 4259 | 0 | 80031 | 0 | 0 | 0 | 25 | 406538 | 80100 | 164256 | 160000 | 80100 | 160000 | 160000 | 480499 | 2078874 | 1301899 | 0 | 80023 | 80050 | 80050 | 0 | 3 | 26 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80049 | 80049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 0 | 32 | 0 | 0 | 160000 | 0 | 0 | 2 | 160002 | 2 | 32 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80047 | 80000 | 160000 | 160000 | 80100 | 80061 | 80046 | 80047 | 80050 | 80046 |
320204 | 80045 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5971 | 0 | 80029 | 0 | 16 | 0 | 25 | 404672 | 80100 | 164746 | 160000 | 80100 | 160000 | 160000 | 480499 | 2078919 | 1287263 | 0 | 80023 | 80050 | 80049 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80049 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 0 | 32 | 0 | 0 | 160002 | 0 | 0 | 5 | 160002 | 2 | 32 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80047 | 80000 | 160000 | 160000 | 80100 | 80045 | 80051 | 80045 | 80045 | 80045 |
320204 | 80050 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 1 | 5907 | 0 | 80029 | 16 | 15 | 0 | 25 | 401923 | 80100 | 165152 | 160000 | 80100 | 160000 | 160000 | 480499 | 2399916 | 1280035 | 0 | 80025 | 80057 | 80050 | 0 | 3 | 34 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80049 | 80049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160013 | 13 | 38 | 0 | 0 | 160014 | 0 | 0 | 14 | 160002 | 14 | 38 | 12 | 1 | 5109 | 1 | 17 | 1 | 1 | 80046 | 80000 | 160000 | 160000 | 80100 | 80051 | 80051 | 80050 | 80052 | 80050 |
320204 | 80061 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | 5636 | 2 | 80044 | 16 | 0 | 0 | 25 | 405231 | 80100 | 166145 | 160000 | 80100 | 160000 | 160000 | 480499 | 2399741 | 1316426 | 0 | 80025 | 80061 | 80061 | 0 | 3 | 31 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80050 | 80057 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160012 | 13 | 38 | 0 | 0 | 160012 | 0 | 1 | 15 | 160002 | 12 | 38 | 12 | 1 | 5109 | 1 | 17 | 1 | 1 | 80049 | 80000 | 160000 | 160000 | 80100 | 80060 | 80051 | 80051 | 80049 | 80051 |
320204 | 80050 | 621 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | 4700 | 2 | 80044 | 16 | 16 | 0 | 25 | 406145 | 80100 | 164706 | 160067 | 80100 | 160000 | 160000 | 480499 | 2319855 | 1296121 | 0 | 80034 | 80052 | 80048 | 0 | 3 | 32 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80050 | 80050 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160012 | 13 | 38 | 0 | 1 | 160014 | 0 | 0 | 14 | 160002 | 14 | 38 | 12 | 0 | 5109 | 1 | 17 | 1 | 1 | 80047 | 80000 | 160000 | 160000 | 80100 | 80071 | 80052 | 80051 | 80062 | 80062 |
320204 | 80051 | 620 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 16 | 0 | 0 | 1 | 4700 | 2 | 80046 | 16 | 16 | 0 | 25 | 402781 | 80100 | 162681 | 160000 | 80100 | 160000 | 160000 | 480499 | 3679174 | 1308227 | 0 | 80036 | 80051 | 80050 | 0 | 3 | 43 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80061 | 80050 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160012 | 13 | 37 | 0 | 1 | 160014 | 0 | 0 | 17 | 160002 | 14 | 36 | 12 | 0 | 5109 | 1 | 17 | 1 | 1 | 80048 | 80000 | 160000 | 160000 | 80100 | 80060 | 80051 | 80063 | 80062 | 80061 |
320204 | 80050 | 620 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 18 | 0 | 0 | 1 | 4975 | 2 | 80035 | 16 | 16 | 0 | 25 | 402534 | 80100 | 164728 | 160000 | 80100 | 160000 | 160000 | 480499 | 2319939 | 1299241 | 0 | 80025 | 80050 | 80061 | 0 | 3 | 31 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80061 | 80050 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160012 | 12 | 38 | 0 | 0 | 160014 | 0 | 1 | 14 | 160000 | 12 | 37 | 12 | 3 | 5109 | 1 | 17 | 1 | 1 | 80048 | 80000 | 160000 | 160000 | 80100 | 80058 | 80062 | 80052 | 80051 | 80050 |
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 37 | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320027 | 80045 | 621 | 0 | 0 | 1 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 4139 | 80030 | 0 | 16 | 0 | 25 | 402061 | 80010 | 162789 | 160000 | 80010 | 160000 | 160000 | 480401 | 2145910 | 1300400 | 80023 | 80044 | 80044 | 0 | 3 | 28 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80045 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 0 | 42 | 4 | 5019 | 12 | 17 | 6 | 14 | 80041 | 80000 | 160000 | 160000 | 80010 | 80046 | 80045 | 80045 | 80046 | 80046 |
320024 | 80045 | 621 | 0 | 1 | 0 | 0 | 0 | 132 | 95 | 1 | 0 | 0 | 3996 | 80029 | 16 | 0 | 0 | 25 | 403916 | 80010 | 165121 | 160000 | 80010 | 160000 | 160000 | 480049 | 2079414 | 1303195 | 80407 | 80045 | 80044 | 0 | 3 | 26 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80044 | 80044 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 42 | 0 | 0 | 160002 | 0 | 2 | 2 | 160002 | 2 | 40 | 0 | 5019 | 12 | 17 | 6 | 13 | 80197 | 80000 | 160000 | 160000 | 80010 | 80047 | 80045 | 80214 | 80045 | 80046 |
320024 | 80044 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 4329 | 80029 | 0 | 16 | 0 | 25 | 402061 | 80010 | 165626 | 160000 | 80010 | 160000 | 160000 | 480049 | 2079721 | 1303151 | 80025 | 80045 | 80044 | 0 | 3 | 26 | 400295 | 20 | 160000 | 160000 | 20 | 400000 | 320272 | 80045 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 40 | 0 | 2 | 160002 | 0 | 0 | 2 | 160002 | 2 | 40 | 0 | 5019 | 13 | 17 | 13 | 12 | 80040 | 80000 | 160000 | 160000 | 80010 | 80045 | 80046 | 80046 | 80046 | 80046 |
320024 | 80045 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 3968 | 80029 | 0 | 16 | 0 | 25 | 404288 | 80010 | 166611 | 160000 | 80010 | 160000 | 160000 | 480049 | 2099739 | 1295316 | 80024 | 80045 | 80044 | 85 | 3 | 26 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80044 | 80046 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 40 | 0 | 0 | 160002 | 0 | 0 | 922 | 160002 | 2 | 40 | 0 | 5019 | 13 | 17 | 8 | 14 | 80041 | 80000 | 160000 | 160000 | 80010 | 80045 | 80046 | 80213 | 80047 | 80047 |
320024 | 80046 | 620 | 0 | 0 | 0 | 0 | 0 | 21 | 3 | 0 | 0 | 0 | 5362 | 82693 | 16 | 0 | 0 | 25 | 402352 | 80010 | 165813 | 160000 | 80010 | 160000 | 160108 | 480049 | 2155312 | 1303217 | 80030 | 80044 | 80044 | 84 | 3 | 27 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80045 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 0 | 0 | 160000 | 1 | 0 | 2 | 160000 | 10 | 42 | 0 | 5019 | 13 | 17 | 14 | 14 | 80041 | 80000 | 160000 | 160000 | 80010 | 80046 | 80045 | 80045 | 80046 | 80046 |
320024 | 80045 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4752 | 80029 | 0 | 16 | 0 | 25 | 402259 | 80010 | 166158 | 160000 | 80010 | 160000 | 160000 | 480049 | 2237556 | 1304480 | 80023 | 80044 | 80054 | 0 | 3 | 27 | 400295 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80045 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 40 | 0 | 0 | 160062 | 0 | 0 | 2 | 160002 | 2 | 40 | 0 | 5019 | 12 | 25 | 13 | 13 | 80042 | 80000 | 160000 | 160000 | 80010 | 80046 | 80045 | 80047 | 80047 | 80046 |
320024 | 80052 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 91 | 1 | 0 | 0 | 3941 | 80030 | 16 | 16 | 0 | 25 | 403858 | 80010 | 164463 | 160000 | 80010 | 160000 | 160000 | 480049 | 2236529 | 1293745 | 80487 | 80044 | 80054 | 0 | 3 | 27 | 400010 | 20 | 160000 | 160120 | 20 | 400000 | 320000 | 80044 | 80047 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 40 | 0 | 0 | 160002 | 0 | 0 | 0 | 160062 | 6 | 40 | 0 | 5019 | 13 | 17 | 12 | 6 | 80051 | 80000 | 160000 | 160000 | 80010 | 80211 | 80045 | 80045 | 80045 | 80045 |
320024 | 80046 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 6476 | 80198 | 16 | 16 | 0 | 25 | 403846 | 80010 | 163783 | 160000 | 80069 | 160000 | 160000 | 480049 | 2079671 | 1292988 | 80024 | 80045 | 80211 | 0 | 3 | 27 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80046 | 80044 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 40 | 0 | 0 | 160002 | 1 | 0 | 2 | 160002 | 6 | 0 | 0 | 5019 | 13 | 17 | 14 | 15 | 80041 | 80000 | 160000 | 160000 | 80010 | 80046 | 80045 | 80055 | 80046 | 80046 |
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